ViewSonic VS11446 Service Manual page 18

Embedded OSD
 E mbedded 12K SRAM dynamically stores OSD
 S upp ort multi-color RAM font, 1, 2 and 4-bit per pixel
 1 6 color palette with 24bit true color selection
 M aximum 8 window with alpha
window type
 R otary 90,180,270 degree
 I ndependent r
 P rogrammable blinking effects for each character
 O SD -made internal pattern generator for factory mode
 S upport 12x18~4x18 proportional font
 D ecompress OSD font
Power & Technology
 3 .3V power supplier
 0 .18um CMOS process, 12
 E mbedded 3.3V to 1.8V voltage regulator
Analog Input
RTD integrates three ADC＇s (analog-to-digital converters), one for each color (red, green, and blue).
The sync-processor can deal with Separate-Sync, Composite-Sync, and Sync-On-Green. And the PLL
can generate very low jitter clock from HS to sample the analog signal to digital data. Input data is
latched within a capture window defined in registers refer to VS and HS leading edge. RTD also has 2
ADC input, we can switch these 2 input to choose which input we want to present on RTD embedded
LCD monitor.
RTD has a YPbPr input, we can connect DVD or some devices that has YPbPr input, YPbPr input can
be 1st or 2nd ADC pins.
TMDS Input
RTD integrates high-speed single link receiver function. It can operate up to 165 M at long cable. RTD
integrates an equalizer to enhance the cable loss weakness in long cable application and the advanced
tracking algorithm to have better performance in DVI RX.
Display Output Timing
The display output port sends single/double pixel data transfer and synchronized display timing to an
external device. The display port also support display panel with 6-bit per color, turn on the dithering
function to enhance color depth. In single pixel output mode, single pixel data (24-bit RGB) is
transferred to display port A on each active edge of DCLK, the rate of DCLK is also equal to display
pixel clock. The sync & enable signals are also sent to display port on each active edge of DCLK. In
double pixel output mode, double pixel data (48-bit RGB) is transferred to display port A & B on each
active edge of DCLK and the rate of DCLK is equal to half display pixel clock at this moment.
The sync & enable signals are also sent to display port on each active edge of DCLK.
Color Processing
Digital color R & G & B independent channel sRGB, contrast, brightness, gamma, dithering controls
are built in RTD. sRGB compliance function is provided with 9 multipliers. The contrast control is
performed a multiply value from 0 to 2 for each R/G/B channel. The brightness control is used to set an
offset value from –512 to +511 also for each R/G/B channel. Also RTD provided 10 bit gamma and a
high performance dithering function.
Build-In OSD
The detailed function-description of build-in OSD, please refer to the application note for RTD
embedded OSD.
Color LUT & Overlay Port
The following diagram presents the data flow among the gamma correction, dithering, overlay MUX,
OSD LUT and output format conversion blocks.
Auto-Adjustment
There are two main independent auto-adjustment functions supported by RTD, including
auto-position & auto-tracking. The operation procedure is as following;
ViewSonic Corporation
-blending/gradient/dynamic fade-in/fade-out, bordering/shadow/3D
ow shadowing/bordering
8-pin QFP package
command and fonts
15
Confidential - Do Not Copy
VX2235wm-4