Sony STR-DA3100ES Service Manual page 80

STR-DA3100ES
DIGITAL BOARD IC2251 CXD9782R (DSP2)
Pin No. Pin Name
1 VDDI
2 EXTIN
3, 4 WMD1, WMD0
5 MOD1
6 MOD0
7 VSS
8 XRST
9 VSS
10 SCKOUT
11 VDDI (PLL)
12 SYNC
13 to 15 PAGE2 to PAGE0
16 PLOCK
17 BTACK
18 VDDE
19 VSS
20 to 22 D31 to D29
23 A17
24 VSS
25, 26 SDO3, SDO4
27, 28 SDI1, SDI2
29 LRCKI1
30 VSS
31, 32 D28, D27
33 A16
34 A15
35 SDI3
36 L2
37 VDDI
38 BCKI1
39 SDI4
40 MS
41, 42 A14, A13
43, 44 D26, D25
45 VSS
46 BCKI2
47, 48 FS2, FS1
49 SPDIF
50 A12
51 to 53 D24 to D22
54 VDDE
55 VSS
56 to 58 D21 to D19
59 A11
60, 61 SDO1, SDO2
62 KFSIO
80
I/O
– Power supply terminal (+2.6V)
I Master clock signal input terminal Not used
I External memory wait mode setting terminal Fixed at "H" in this set
Operation mode setting terminal "L": enhanced mode, "H": normal mode
I
Fixed at "H" in this set
Operation mode setting terminal "L": single chip mode, "H": can not use
I
Fixed at "L" in this set
– Ground terminal
I System reset signal input from the main system controller "L": reset
– Ground terminal
O Internal serial clock signal output terminal Not used
– Power supply terminal (+2.6V) (for PLL)
I Sync/non-sync setting terminal "L": sync, "H": non-sync Fixed at "H" in this set
O External memory page selection signal output terminal Not used
O Internal PLL lock signal output terminal Not used
O Boot mode state display signal output terminal Not used
– Power supply terminal (+3.3V)
– Ground terminal
I/O Two-way data bus with the S-RAM
O Address signal output terminal Not used
– Ground terminal
O Audio serial data output to the lip sync adjust
I Audio serial data input from the DSP1
I L/R sampling clock signal (44.1 kHz) input from the DSP1
– Ground terminal
I/O Two-way data bus with the S-RAM
O Address signal output terminal Not used
O Address signal output to the S-RAM
I Audio serial date input from the DSP1
– Not used
– Power supply terminal (+2.6V)
I Bit clock signal (2.8224 MHz) input from the DSP1
I Audio serial data input from the DSP1
Master/slave setting terminal "L": internal clock, "H": external clock
I
Fixed at "L" in this set
O Address signal output to the S-RAM
I/O Two-way data bus with the S-RAM
- Ground terminal
I Bit clock signal (2.8224 MHz) input terminal Not used
I Sampling frequency selection signal input terminal Not used
I SPDIF signal input terminal Not used
O Address signal output to the S-RAM
I/O Two-way data bus with the S-RAM
– Power supply terminal (+3.3V)
– Ground terminal
I/O Two-way data bus with the S-RAM
O Address signal output to the S-RAM
O Audio serial data output to the lip sync adjust
I Audio clock signal input terminal
Description