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CP-850/F Service Manual
4.3 DDP 3315C - DISPLAY AND DEFLECTION PROCESSOR
The DDP 3315C is a mixed-signal single-chip digital display and deflection processor, designed
for high-quality backend applications in double scan and HDTV TV sets with 4:3 or 16:9 picture
tubes. The interfaces qualify the IC to be combined with state of the art digital scan rate
converters, as well as analog HDTV sources. The DDP 3315C contains the entire digital video
component, deflection processing, and all analog interfaces to display the picture on a CRT.
4.3.1 BLOCK DIAGRAM OF THE DDP 3315C
LLC
Clock
27/32/
Generator
54 MHz
Y
Y /
Input
656 YCrCb
Cb
Interface
Cr
CrCb
4:2:2 /
4:1:1
2
I
C
SDA
Interface
SCL
General
purpose
PWM
PWM 1/2
Y
Y
Upcon-
Picture
Cb
Cb
Version/
Improve-
Cr
Cr
Scaling
ment
EHT
V
Sync
Display-
Pro-
Freq.
H
cessing
Doubling
2H / 2V
FIFO
(1H / 1V)
Controlling
SVM
SVM
R
R
Matrix /
Video
G
G
PFG /
DAC
B
B
NCE
V
Sawtooth /
V
Parabola
EW
Generation
H-Drive
H
H
Generation
HFLB
-26-
analog
RGB-
Matrix
R
Analog
Tube
G
RGB
Control
B
Switch
V
H & V
EW
H / V
dynamic
Security
focus
H
Unit
DFVBL
VPROT
PWMV
HSAFETY
Pr
Y
Input
Pb
FBL
R
G
Output
B
Sense
Input
VERT+
VERT
E/W
HOUT
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