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4.1.3 IC MARKING AND VERSION
Chassis
IC marking
CP-850/F
4.1.4 PINNING
PSDIP 52-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OSD languages
AUSTRALIA, BULGARIAN,
CZECH, GERMAN,
DANISH, SPANISH,
FRENCH, FINNISH,
GREEK,
HUNGARIAN,
ITALIAN,
NORWEGIAN,
DUTCH, POLISH,
ROMANIAN,
RUSSIAN,
SWEDISH,
Pin Name
Type
SCL
IN/OUT
SDA
IN/OUT
S/SW2
IN
S/SW2
IN
OCP
IN
n.c.
n.c.
Reset Out
OUT
VDD2.5
IN
VSS
IN
VDD3.3
IN
CVBS
IN
VDDA2.5
IN
VSSA
IN
S/SW1
IN
AGC
IN
KEY
IN
AFT
IN
HS
IN
VS
IN
MODESW
OUT
L/L'
OUT
IR
IN
INT
IN
ATSS countries
Australia, Austria, Belgium,
Switzerland, Czech
Republic, Germany,
Denmark, Spain,
France, Finland, GB,
Greece, Hungary, Italy,
Ireland, Norway,
Netherlands, Portugal,
Poland, Sweden,
Others
Short Description
Software driven I2C bus Clock line
Software driven I2C bus Data line
Slow switching control for SCART 2.
(See Microcontroller I/O pin configuration)
Switch Off the set when the voltage goes below a trigger level
Driven by controlling software to reset video IC's.
Supply voltage 2.5V
Ground (0V)
Input/Output 3.3V
CVBS input for the acquisition circuit
Supply voltage for analog components
Ground for analog components
Slow switching control for SCART 1.
ADC input, for AGC alignment only
ADC input, local key sensing
ADC input, AFT input
Horizontal sync for OSD/Txt synchronisation
Vertical sync for OSD/Txt synchronisation
High : Negative video modulation (B, G, D, K,I)
Low : Positive video modulation (L / L')
High : L', Low : L
Remote control signal input
Interrupt input from audio processor
-17-
CP-850/F Service Manual
Text
PAN-EUROPEAN
LATIN, CYRILLIC,
GREEK.
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