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A-1,A0 to A21
DQ0 to DQ15
CE1
, CE2
ps
ps
CEf1 , CEf2
OE
WE
LB , UB
WP/ACC
RESET
BYTE
RY/ BY
Vcc
ps
Vcc
f
Vss
DU
NC
Table 3-8 Pin Description of U201.
Address inputs
Data inputs / outputs
Chip enable inputs for Pseudo SRAM
Chip enable inputs for Nor Flash Memory
Output enable input
Write enable input
Data byte control inputs for Pseudo SRAM
Write protect /program acceleration input for Nor Flash Memory
Hardware reset input for Nor Flash Memory
Word/Byte onput for Nor Flash Memory
Ready/Busy output for Nor Flash Memory
power supply for Pseudo SRAM
power supply for Nor Flash Memory
Ground
Don't use
Not connected
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3. TECHNICAL BRIEF
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