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3. TECHNICAL BRIEF
DCS TX
GSM TX
GSM/DCS RX
Three differential-input LNAs are integrated in SI4205. The GSM input supports the GSM 850 (869-
849 MHz) or E-GSM 900 (925-960MHz) bands. The DCS input supports the DCS 1800 (1805-1880
MHz) band. The PCS input supports the PCS 1900 (1930-1990 MHz) band.
The LNA inputs are matched to the 150Ω balanced output SAW filters through external LC matching
networks. The LNA gain is controlled with the LNAG[1:0] and LNAC[1:0] bits in register 05h (Figure 3-
2).
B. Intermediate frequency (IF) and Demodulation
A quadrature image-reject mixer downconverts the RF signal to a 100KHz intermediate frequency (IF)
with the RFLO from the frequency synthesizer. The RFLO frequency is between 1737.8 to 1989.9
MHz, and is internally divided by 2 for GSM 850 and E-GSM 900 modes. The mixer output is amplified
with an analog programmable gain amplifier (PGA), which is controlled with the AGAIN[2:0] bits in
register 05h (Figure3-2). The quadrature IF signal is digitized with high resolution A/D converters
(ADCs).
The ADC output is downconverted to baseband with a digital 100KHz quadrature LO signal. Digital
decimation and IIR filters perform channel selection to remove blocking and reference interference
signals. The selectivity setting (CSEL=0) or a low selectivity setting (CSEL=1). The low selectivity filter
has a flatter group channelization filter is in the baseband chip. After channel selection, the digital
output is scaled with a digital PGA, which is controlled with the DGAIN [5:0] bits in register 05h.
The amplified digital output signal go through with DACs that drive a differential analog signal onto the
RXIP,RXIN,RXQP and RXQN pins to interface to standard analog ADC input baseband ICs. No
Table 3-1 The Logic and current
VC1
OV
2.5 ~ 3.0V
0V
Figure 3-2 Block Diagram of Receiver part of SI4205
VC2
2.5 ~ 3.0V
0V
0V
- 14 -
Current
10.0 mA max
10.0 mA max
< 0.1 mA
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