Sony MDX-C8500R Service Manual page 42

• IC Block Diagrams
– SERVO Board –
IC301 CDX2652AR
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PWM
SPINDLE
GENERATOR
SERVO
MNT0 1
MNT1 2
MONITOR EACH
CONTROL BLOCK
MNT2 3
MNT3 4
ADIP
DECODER
SWDT 5
SCLK 6
EACH
CPU I/F
XLAT 7
BLOCK
SERVO
SRDT 8
DSP
SENS 9
XRST 10
SQSY 11
SUBCODE
PROCESSOR
DQSY 12
RECP 13
SHOCK RESISTANT
XINT 14
MEMORY CONTROLLER
TX 15
16
OSCI
CLOCK EACH
OSCO 17
GENERATOR BLOCK
XTSL 18
DIGITAL SAMPLING
NC 19
AUDIO RATE
DVSS 20
I/F CONVERTER
DIN 21
DOUT 22
ADDT 23
ATRAC
ENCODER/DECODER
DADT 24
LRCK 25
ADDRESS/DATA BUS A00 - A11, D0 - D3
26 27 28 29 30 31 32 33 34 35 36 37 38 39
75 AUX2
74 TE
73 SE
72 AVSS
71 ADRB
70 ADRT
69 AVDD
68 ADIO
67 VC
A/D
66 AUX1
CONVERTER
65 FE
ANALOG
MUX
64 ABCD
63 BOTM
62 PEAK
61 CLTV
60 FILO
59 FILI
58 PCO
57 PDO
56 AVSS
55 RFI
COMP
54 BIAS
53 AVDD
52 ASYI
51 ASYO
40 41 42 43 44 45 46 47 48 49 50
IC302 CXA2523AR
48 47 46 45
RFA1
RFA2
I 1 – HLPT
1
–
–
2
J 2 –
OFST
–
1
–
2
CVB
–
VC 3
GRV
GRVA
+
A 4
–
AA
IVR
+
B 5
–
BB
IVR
+
C 6
–
CC
IVR
D 7 +
–
DD
IVR
+
E 8
+
–
EE
IVR
–
EBAL
+
F 9
+
–
IVR FF
–
IV
FBAL
GSW
PD 10
+ –
+ –
APC 11
APCREF 12
13 14
42 42
44 43 42 41 40 39 38 37
USROP
–
+ RF AGC EQ
+
–
USRC
DET EQ
BPF3T
RFA3
AUX
PEAK3T
–1 SW
3T
P-P
–2
3T WBL
PTGR
TEMP
PEAK
–2
BOTTOM 36 BOTM
PBH
–1
PBSW
WBL
35 ABCD
34 FE
–
33 AUX
–
–
– BPFC
ABCDA
32 ADFG
31 ADAGC
+
+
30 ADIN
–
– FEA
DET
BPF22
–
ADIP
–
WBL 29 ADFM
+
AGC
+ ATA
WBL
–1 TG
28 SE
PTGR
– –2
SEA
+
EE'
–
27 CSLED
+
–1
EFB TESW TG
26 TE
–2
TEA
ESW
WBL
FF'
25 WBLADJ
3T VI CONV
EQ
AUXSW
BGR
COMMAND
VREF
SCRI - PARA
DECODE
15 16 17 18 19 20 21 22 23 24