Daewoo DTH-25G1FST/FSP/FS Service Manual page 22

♦ I601
- CX A2104S (US AUDIO M ULTIPLEXIN G D ECODER )
1. PIN DESC RIPTION
SYM BOL PIN
R O U T 1 T V O U T right channel output pin.
L O U T 2 T V O U T left channel output pin.
S DA 3 S erial data I/O pin.
S CL 4 S erial clock I/O pin.
D .G N D 5 D igital block ground.
M AIN IN 6 Input the (L+R) signal from M A IN O U T (pin 7)
M AIN O UT 7 (L+R ) signal output pin.
P CIN T 1 8 S tereo block P LL loop filter integrating pin.
P CIN T 2 9
P LIN T 10 P ilot cancel circuit loop filter integrating pin.
C O M P IN 11 A udio m ultiplexing signal input pin.
V G R 12 B and gap reference output pin.(connect a 10µF capacitor betw een this pin and G N D .)
IRE F 13 S et the filter and V CO reference current.
G ND 14 A nalog block G N D .
S AP TC 15 S et the tim e constant for the S A P carrier detection circuit.
V cc 16 S upply voltage pin.
S UB O U T 17 (L-R ) signal output pin.
S TIN 18 Input the (L-R) signal from S U B O U T (pin 17).
N O IS E T C 19 S et the tim e constant for the noise detection circuit.(connect a 47µF C apacitor B etw een this pin and
G N D.)
S AP O U T 20 S A P FM detector output pin.
S AP IN 21 Input the (S AP ) signal from S A P O U T (pin 20).
V E 22 Variable de-em phasis integrating pin.(connect a 2700pF capacitor and a 3.3kΩ R esistor in series
betw een this pin and G N D .)
V EW G T 23 W eight the variable de-em phasis control effective value detection circuit.
V ET C 24 D eterm ine the restoration tim e constant of the variable de-em phasis control
E ffective value detection circuit.
V EO U T 25 Variable de-em phasis output pin.(connect a 4.7µF non-polar capacitor betw een Pins 25 and 26.)
V CA IN 26 V C A input pin.
V CATC 27 D eterm ine the restoration tim e constant of the VC A control effective value D etection circuit.
V CAW G T 28 W eight the V C A control effective value detection circuit.(connect a 1µF capacitor A nd a 3.9kΩ
resistor in series betw een this pin and G ND .)
N .C 29 N .C
S O U T 30 N .C
DESCRIPTION

IC DESCRIPTION