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Intel GD82559ER Datasheet

Fast ethernet** pci controller
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GD82559ER Fast Ethernet**
PCI Controller
Networking Silicon

Product Features

Optimum Integration for Lowest Cost
Solution
— Integrated IEEE 802.3 10BASE-T and
100BASE-TX compatible PHY
— Glueless 32-bit PCI master interface
— 128 Kbyte Flash interface
2
— Thin BGA 15mm
package
— ACPI and PCI Power Management
— Power management event on
"interesting" packets and link status
change support
— Test Access Port
Datasheet
High Performance Networking Functions
— Chained memory structure similar to the
82559,82558, 82557, and 82596
— Improved dynamic transmit chaining
with multiple priorities transmit queues
— Full Duplex support at both 10 and 100
Mbps
— IEEE 802.3u Auto-Negotiation support
— 3 Kbyte transmit and 3 Kbyte receive
FIFOs
— Fast back-to-back transmission support
with minimum interframe spacing
— IEEE 802.3x 100BASE-TX Flow
Control support
— Low Power Features
— Low power 3.3 V device
— Efficient dynamic standby mode
— Deep power down support
— Clockrun protocol support
Document Number: 714682-001
Revision 1.0
March 1999

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Summary of Contents for Intel GD82559ER

  • Page 1: Product Features

    GD82559ER Fast Ethernet** PCI Controller Networking Silicon Product Features Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — Glueless 32-bit PCI master interface — 128 Kbyte Flash interface — Thin BGA 15mm package —...

  • Page 2: Revision History

    Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    3.2.3 System and Power Management Signals... 9 Local Memory Interface Signals ... 9 Testability Port Signals ...10 PHY Signals ...11 GD82559ER MEDIA ACCESS CONTROL FUNCTIONAL DESCRIPTION ...13 82559ER Initialization ...13 4.1.1 Initialization Effects on 82559ER Units ...13 PCI Interface...14 4.2.1 82559ER Bus Operations...14...
  • Page 4 GD82559ER — Networking Silicon 6.1.2 100BASE-TX Transmit Blocks ... 37 6.1.3 100BASE-TX Receive Blocks ... 40 6.1.4 100BASE-TX Collision Detection ... 41 6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution... 41 6.1.6 Auto 10/100 Mbps Speed Selection ... 41 10BASE-T Functionality ... 41 6.2.1...
  • Page 5 10.4 Timing Specifications...77 10.4.1 Clocks Specifications ...77 10.4.2 Timing Parameters ...78 PACKAGE AND PINOUT INFORMATION ...85 12.1 Package Information...85 12.2 Pinout Information ...86 12.2.1 GD82559ER Pin Assignments ...86 12.2.2 GD82559ER Ball Grid Array Diagram ...88 Datasheet Networking Silicon — GD82559ER...
  • Page 6 GD82559ER — Networking Silicon Datasheet...

  • Page 7: Introduction

    Introduction GD82559ER Overview The 82559ER is part of Intel's second generation family of fully integrated 10BASE-T/100BASE- TX LAN solutions. The 82559ER consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution. 82559 family members build on the basic functionality of the 82558 and contain power management enhancements.
  • Page 8 GD82559ER — Networking Silicon Datasheet...

  • Page 9: Gd82559Er Architectural Overview

    Local Memory Interface PCI Target and 3 Kbyte Flash/EEPROM Tx FIFO Interface FIFO Control Micro- machine 3 Kbyte Dual Rx FIFO Ported FIFO Figure 1. 82559ER Block Diagram Networking Silicon — GD82559ER 100BASE-TX/ 10/100 Mbps T P E 10BASE-T CSMA/CD Interface...

  • Page 10: Fifo Subsystem Overview

    GD82559ER — Networking Silicon operate independently. Control is switched between the two units according to the microcode instruction flow. The independence of the Receive and Command units in the micromachine allows the 82559ER to interleave commands and receive incoming frames, with no real-time CPU intervention.

  • Page 11: 10/100 Mbps Serial Csma/Cd Unit Overview

    100BASE-TX Half Duplex, 10BASE-T Full Duplex, and 10BASE-T Half Duplex. It also supports three LED pins to indicate link status, network activity, and speed.The 82559ER does not support external PHY devices and does not expose its internal MII bus. Datasheet Networking Silicon — GD82559ER...
  • Page 12 GD82559ER — Networking Silicon Datasheet...

  • Page 13: Signal Descriptions

    TRDY# is asserted on a read transaction.Once PAR is valid, it remains valid until one clock after the completion of the current data phase. The master drives PAR for address and write data phases; and the target, for read data phases. Networking Silicon —GD82559ER Description...

  • Page 14: Interface Control Signals

    GD82559ER — Networking Silicon 3.2.2 Interface Control Signals Symbol FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# REQ# GNT# INTA# SERR# PERR# Type Name and Function Cycle Frame. The cycle frame signal is driven by the current master to indicate the beginning and duration of a transaction. FRAME# is...

  • Page 15: System And Power Management Signals

    During EEPROM accesses, it acts as the serial shift clock output to the EEPROM. Flash Address[14]/EEPROM Data Output. During Flash accesses, this multiplexed pin acts as the Flash Address [14] output signal. IN/OUT During EEPROM accesses, it acts as serial input data to the EEPROM Data Output signal. Networking Silicon —GD82559ER...

  • Page 16: Testability Port Signals

    GD82559ER — Networking Silicon Symbol FLA[13]/ EEDI FLA[12:8] FLA[7]/ CLKENB FLA[6:2] FLA[1]/ AUXPWR FLA[0] EECS FLCS# FLOE# FLWE# Testability Port Signals Symbol TEST TEXEC Type Name and Function Flash Address[13]/EEPROM Data Input. During Flash accesses, this multiplexed pin acts as the Flash Address [13] output signal.

  • Page 17: Phy Signals

    Voltage Reference. This pin is connected to a 1.25 V ± 1% external voltage reference generator. To use the internal voltage reference source, this pin should be left floating. for the RBIAS100 and RBIAS10, respectively, are only a recommended values and Networking Silicon —GD82559ER pull- pull-down...
  • Page 18 GD82559ER — Networking Silicon Datasheet...

  • Page 19: Gd82559Er Media Access Control Functional Description

    GD82559ER Media Access Control Functional Description 82559ER Initialization The 82559ER has four sources for initialization. They are listed according to their precedence: 1. ALTRST# Signal 2. PCI RST# Signal 3. Software Reset (Software Command) 4. Selective Reset (Software Command) 4.1.1...

  • Page 20: Pci Interface

    GD82559ER — Networking Silicon PCI Interface 4.2.1 82559ER Bus Operations After configuration, the 82559ER is ready for normal operation. As a Fast Ethernet controller, the role of the 82559ER is to access transmitted data or deposit received data. In both cases the 82559ER, as a bus master device, will initiate memory cycles via the PCI bus to fetch or deposit the required data.
  • Page 21 82559ER with valid data on each data access immediately after asserting IRDY#. The 82559ER Datasheet FRAME# ADDR DATA C/BE# I/O RD IRDY# TRDY# DEVSEL# STOP# Figure 2. CSR I/O Read Cycle FRAME# ADDR DATA C/BE# I/O WR IRDY# TRDY# DEVSEL# STOP# Figure 3. CSR I/O Write Cycle Networking Silicon — GD82559ER...
  • Page 22 GD82559ER — Networking Silicon controls the TRDY# signal and asserts it from the data access. The 82559ER allows the CPU to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal. This is true for both memory mapped and I/O mapped accesses.
  • Page 23 Figure 5. Flash Buffer Write Cycle the control lines IRDY# IRDY# , the 82559ER signals the CPU that the current data access has completed. Networking Silicon — GD82559ER the command and AD[31:0], . It also provides the FRAME# . The 82559ER controls the...
  • Page 24 GD82559ER — Networking Silicon Note: The 82559ER is considered the target in the above diagram; thus, TRDY# is not asserted. 4.2.1.1.4 Error Handling Data Parity Errors: The 82559ER checks for data parity errors while it is the target of the transaction.
  • Page 25 The length of a burst is bounded by the system and the 82559ER’s internal FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA Maximum Byte Count in the Configure command. The Transmit DMA Maximum Datasheet Networking Silicon — GD82559ER ADDR DATA DATA...
  • Page 26 GD82559ER — Networking Silicon Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after an 82559ER internal arbitration. (Details on the Configure command are described in the Software Developer’s Manual.) The 82559ER, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#.
  • Page 27 When the arbitration counter’s feature is enabled (in other words, the Transmit DMA Maximum Byte Count value is set in the Configure command), the 82559ER switches to other pending DMAs on the cache line boundary only. Note the following: Datasheet Networking Silicon — GD82559ER...

  • Page 28: Clockrun Signal

    GD82559ER — Networking Silicon • This feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. • This feature should be used only when the CLS register in PCI Configuration space is set to 8 or 16 Dwords.

  • Page 29: Power States

    The 82559ER will not attempt to keep the link alive by transmitting idle symbols or link integrity pulses. The sub-10 mA state due to an invalid link can be enabled or disabled by a configuration bit in the Power Management Driver Register (PMDR). Datasheet Networking Silicon — GD82559ER state, cold Section 4.2.5, “Wake-up Events”...
  • Page 30 GD82559ER — Networking Silicon 4.2.4.4 D3 Power State In the D3 power state, the 82559ER has the same capabilities and consumes the same amount of power as it does in the D2 state. However, it enables the PCI system to be in the B3 state. If the PCI system is in the B3 state (in other words, no PCI power is present), the 82559ER provides wake-up capabilities if it is connected to an auxiliary power source in the system.
  • Page 31 RST# and CLK signals. It also tri-states all PCI outputs, except the PME# signal. In the transition to an active PCI power state (in other words, from B3 power state to B0 power state), the PCI power good signal shifts high. Datasheet Networking Silicon — GD82559ER Link 82559ER Functionality •...
  • Page 32 GD82559ER — Networking Silicon In a LAN on Motherboard solution, the PCI power good signal is supplied by the system. In network adapter implementations, the PCI power good signal can be either generated locally using an external analog device, or connected directly to the PCI reset signal. In designs, that use both the ISOLATE# and RST# pins of the 82559ER, the PCI power good signal should envelope ISOLATE#, as shown below.

  • Page 33: Wake-Up Events

    128 bytes. Datasheet D0 - D2 power state D3 power state Internal reset due to ISOLATE# Figure 10. 82559ER Initialization upon PCI RST# and ISOLATE# 55.) Networking Silicon — GD82559ER 640 ns 640 ns Section 7.1.19, “Power Management...

  • Page 34: Parallel Flash Interface

    GD82559ER — Networking Silicon 4.2.5.2 Link Status Change Event The 82559ER link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82559ER reports a PME link status event in all power states.
  • Page 35 Figure 11. 64 Word EEPROM Read Instruction Waveform Figure IA Byte 2 IA Byte 4 IA Byte 6 Rev ID Subsystem ID Subsystem Vendor ID Reserved Figure 12. 82559ER EEPROM Format Networking Silicon — GD82559ER IA Byte 1 IA Byte 3 IA Byte 5...

  • Page 36: 10/100 Mbps Csma/Cd Unit

    GD82559ER — Networking Silicon Note that word 0Ah contains several configuration bits. Bits from word 0Ah, FBh through FEh, and certain bits from word 0Dh are described as follows: Word Bits 5:14 Signature Reserved Reserved Boot Disable 10:8 Revision ID...

  • Page 37: Full Duplex

    The 82559ER supports the reception of long frames, specifically frames longer than 1518 bytes, including the CRC, if software sets the Long Receive OK bit in the Configuration command (described in the Software Developer’s Manual). Otherwise, “long” frames are discarded. Datasheet Networking Silicon — GD82559ER...

  • Page 38: Media Independent Interface (Mii) Management Interface

    GD82559ER — Networking Silicon Media Independent Interface (MII) Management Interface The MII management interface allows the CPU to control the PHY unit via a control register in the 82559ER. This allows the software driver to place the PHY in specific modes such as full duplex, loopback, power down, etc., without the need for specific hardware pins to select the desired mode.

  • Page 39: Gd82559Er Test Port Functionality

    GD82559ER Test Port Functionality Introduction The 82559ER’s NAND-Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. The port pro- vides two functions: 1) The the synchronous IC validation mode used in the production of the device.

  • Page 40: Tristate

    GD82559ER — Networking Silicon TriState This command set all 82559ER Input and Output pins into a TRI-state (HIGH-Z) mode, all internal pull-ups and pull-downs are disabled. This mode is entered by setting the following Test Pin Com- binations: TEST = ‘1, TCK = ‘0, TEXEC = ‘0, Nand - Tree The NAND-Tree test mode is the most useful of the asynchronous test modes.
  • Page 41 Chain Order NAND-Tree Output Datasheet Networking Silicon — GD82559ER Table 2. Nand - Tree Chains Chain 1 STOP# GNT# PERR# AD16 C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 C/BE0# FLA13/EEDI FLA14/EEDO FLA15/EESK EECS FLOE# Chain 2 FLD2 FLD3 FLD4 FLD5...
  • Page 42 GD82559ER — Networking Silicon Datasheet...

  • Page 43: Gd82559Er Physical Layer Functional Description

    GD82559ER Physical Layer Functional Description 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its internal transmit digital clocks from this crystal or oscillator input. The internal Transmit Clock signal is a derivative of the 25 MHz internal clock.
  • Page 44 GD82559ER — Networking Silicon Symbol 6.1.2.2 100BASE-TX Scrambler and MLT-3 Encoder Data is scrambled in 100BASE-TX to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The PHY unit implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation.
  • Page 45 10BASE-T mode. The following is a list of current magnetics modules available from several vendors: Vendor Delta Pulse Engineering Pulse Engineering Datasheet Networking Silicon — GD82559ER Figure 13. NRZ to MLT-3 Encoding Diagram Figure 14. Conceptual Transmit Differential Waveform Table 4. Magnetics Modules Model/Type 100BASE-TX LF8200A...

  • Page 46: 100Base-Tx Receive Blocks

    GD82559ER — Networking Silicon 6.1.3 100BASE-TX Receive Blocks The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the PHY unit will accurately receive valid data from Category-5 (CAT5) UTP and Type 1 STP cable of length well in excess of 100 meters.

  • Page 47: 100Base-Tx Collision Detection

    The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The PHY unit provides the transmit clock and receive clock to the internal MAC at 2.5 MHz. Datasheet Networking Silicon — GD82559ER...

  • Page 48: 10Base-T Transmit Blocks

    GD82559ER — Networking Silicon 6.2.2 10BASE-T Transmit Blocks 6.2.2.1 10BASE-T Manchester Encoder After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs the Manchester encoding. The Manchester code always has a mid-bit transition. If the value is 1b then the transition is from low to high.

  • Page 49: 10Base-T Collision Detection

    The possible common modes of operation are: 100BASE-TX, 100BASE-TX Full Duplex, 10BASE-T, and 10BASE-T Full Duplex. Datasheet Networking Silicon — GD82559ER...

  • Page 50: Description

    GD82559ER — Networking Silicon 6.3.1 Description Auto-Negotiation selects the fastest operating mode (in other words, the highest common denominator) available to hardware at both ends of the cable. A PHY’s capability is encoded by bursts of link pulses called Fast Link Pulses (FLPs). Connection is established by FLP exchange and handshake during link initialization time.

  • Page 51: Led Description

    Ready Look at Link Pulse; LINK PASS Auto-Negotiation Complete bit set Figure 15. Auto-Negotiation and Parallel Detect provides possible schematic diagrams for configurations using two and three Networking Silicon — GD82559ER Auto-Negotiation FLP capable Auto-Negotiation capable = 1 Ability Match...
  • Page 52 GD82559ER — Networking Silicon V C C LILED A C T L E D S p e e d L E D 82559ER LILED A C T L E D SpeedLED Figure 16. Two and Three LED Schematic Diagram Datasheet...

  • Page 53: Pci Configuration Registers

    Expansion ROM Base Address Register Reserved Reserved Min_Gnt Interrupt Pin Next Item Ptr Data Power Management CSR Figure 17. PCI Configuration Registers Networking Silicon — GD82559ER Vendor ID Command Revision ID Cache Line Size Subsystem Vendor ID Cap_Ptr Interrupt Line Capability ID...

  • Page 54: Pci Command Register

    GD82559ER — Networking Silicon 7.1.2 PCI Command Register The 82559ER Command register at word address 04h in the PCI configuration space provides control over the 82559ER’s ability to generate and respond to PCI cycles register, the 82559ER is logically disconnected from the PCI bus for all accesses except...

  • Page 55: Pci Status Register

    Received Target Abort Signaled Target Abort 26:25 DEVSEL# Timing Datasheet Networking Silicon — GD82559ER Figure 19. PCI Status Register Table 6. PCI Status Register Bits Description This bit indicates whether a parity error is detected. This bit must be asserted by the device when it detects a parity error, even if parity error handling is disabled (as controlled by the Parity Error Response bit in the PCI Command register, bit 6).

  • Page 56: Pci Revision Id Register

    GD82559ER — Networking Silicon Bits Name Parity Error Detected Fast Back-to-Back Capabilities List 19:16 Reserved 7.1.4 PCI Revision ID Register The Revision ID is an 8-bit read only register with a default value of 08h for the 82559ER. The three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in the EEPROM (Section 4.4, “Serial EEPROM Interface”...

  • Page 57: Pci Latency Timer

    00 - locate anywhere in 32-bit address space 01 - locate below 1 Mbyte 10 - locate anywhere in 64-bit address space 11 - reserved Memory space indicator Datasheet Networking Silicon — GD82559ER Base Address Figure 21. Base Address Register for Memory Mapping 4 3 2 1...
  • Page 58 GD82559ER — Networking Silicon Reserved I/O space indicator Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that map to I/O space must return 1b in bit 0.

  • Page 59: Pci Subsystem Vendor Id And Subsystem Id Registers

    Table 7. 82559ER ID Fields Programming Device ID Vendor ID Revision ID 1209H 8086H 1209H 8086H 1209H 8086H Word AH, bits 10:8 Networking Silicon — GD82559ER Subsystem Subsystem ID Vendor ID 0000H 0000H (Default) (Default) Word BH Word CH Word BH Word CH...

  • Page 60: Interrupt Pin Register

    GD82559ER — Networking Silicon 7.1.13 Interrupt Pin Register The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins, INTA# through INTD#, a PCI device is connected to. The 82559ER is connected the INTA# pin.

  • Page 61: Power Management Control/Status Register (Pmcsr)

    82559ER and to set the 82559ER into a new power state. The definition of the field values is as follows. 00 - D0 01 - D1 10 - D2 11 - D3 Networking Silicon — GD82559ER Description Description...

  • Page 62: Data Register

    GD82559ER — Networking Silicon 7.1.20 Data Register The data register is an 8-bit read only register that provides a mechanism for the 82559ER to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to the Data Select field in the PMCSR register. The power measurements defined in this register have a dynamic range of 0 to 2.55 W with 0.01 W resolution...

  • Page 63: Control/Status Registers

    82559ER to dump information to main memory, or perform an internal self test. The Flash Control register allows the CPU to enable writes to an external Flash. an external EEPROM. Networking Silicon — GD82559ER Lower Word Offset SCB Status Word Early Receive Int...

  • Page 64: System Control Block Status Word

    GD82559ER — Networking Silicon MDI Control Register: Receive DMA Byte Count: Flow Control Register: PMDR: General Control: General Status: 8.1.1 System Control Block Status Word The System Control Block (SCB) Status Word contains status information relating to the 82559ER’s Command and Receive units.

  • Page 65: System Control Block Command Word

    31:30 These bits are reserved and should be set to 00b. Datasheet Networking Silicon — GD82559ER Description Specific Interrupt Mask. Setting this bit to 1b causes the 82559ER to stop generating an interrupt (in other words, de-assert the INTA# signal) on the corresponding event.

  • Page 66: Receive Direct Memory Access Byte Count

    GD82559ER — Networking Silicon Bits Interrupt Enable. When this bit is set to 1b by software, the 82559ER asserts an interrupt to indicate the end of an MDI cycle. Ready. This bit is set to 1b by the 82559ER at the end of an MDI transaction. It should be reset to 0b by software at the same time the command is written.

  • Page 67: General Control Register

    Read Only Speed. This bit indicates the wire speed: 100 Mbps (1b) or 10 Mbps (0b). Read Only Link Status Indication. This bit indicates the status of the link: valid (1b) or invalid (0b). Networking Silicon — GD82559ER Description Description Description...

  • Page 68: Statistical Counters

    GD82559ER — Networking Silicon Statistical Counters The 82559ER provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the 82559ER when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame).
  • Page 69 82559ER that are not Flow Control Pause frames. These frames are valid MAC control frames that have the predefined MAC control Type value and a valid address but has an unsupported opcode. Networking Silicon — GD82559ER Description...
  • Page 70 GD82559ER — Networking Silicon Datasheet...

  • Page 71: Phy Unit Registers

    Enable Power-Down Reserved Datasheet Networking Silicon — GD82559ER Description This bit sets the status and control register of the PHY to their default states and is self-clearing. The PHY returns a value of one until the reset process has completed and accepts a read or write transaction.

  • Page 72: Register 1: Status Register Bit Definitions

    GD82559ER — Networking Silicon Bit(s) Name Restart Auto- Negotiation Duplex Mode Collision Test Reserved 9.1.2 Register 1: Status Register Bit Definitions Bit(s) Name Reserved 100BASE-TX Full Duplex 100 Mbps Half Duplex 10 Mbps Full Duplex 10 Mbps Half Duplex 10:7...

  • Page 73: Register 2: Phy Identifier Register Bit Definitions

    Next Page Acknowledge Remote Fault 12:5 Technology Ability Field Selector Field Datasheet Networking Silicon — GD82559ER Description Value: 02A8H Description Value: 0154H Description Constant 0 = Transmitting primary capability data page This bit is reserved and should be set to 0b.

  • Page 74: Register 6: Auto-Negotiation Expansion Register Bit Definitions

    GD82559ER — Networking Silicon 9.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions Bit(s) Name 15:5 Reserved Parallel Detection Fault Link Partner Next page Able Next Page Able Page Received Link Partner Auto- Negotiation Able MDI Registers 8 - 15 Registers eight through fifteen are reserved for IEEE.

  • Page 75: Register 17: Phy Unit Special Control Bit Definitions

    Squelch Disable Extended Squelch Link Integrity Disable Datasheet Networking Silicon — GD82559ER Description This bit indicates 10BASE-T polarity. 1 = Reverse polarity 0 = Normal polarity These bits are reserved and should be set to 0B. This bit indicates the Auto-Negotiation result.

  • Page 76: Register 18: Phy Address Register

    GD82559ER — Networking Silicon Bit(s) Name Jabber Function Disable 9.3.3 Register 18: PHY Address Register Bit(s) Name 15:5 Reserved PHY Address 9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions Bit(s) Name 15:0 Receive False Carrier 9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions...

  • Page 77: Register 23: 100Base-Tx Receive Premature End Of Frame Error Counter Bit Definitions

    Name 15:3 Reserved LED Switch Control Datasheet Networking Silicon — GD82559ER Description This field contains a 16-bit counter that increments for each premature end of frame event. The counter freezes when full and self-clears on read. Description This is a 16-bit counter that increments for each end of frame error event.
  • Page 78 GD82559ER — Networking Silicon Datasheet...

  • Page 79: Electrical And Timing Specifications

    Table 15. General DC Specifications Condition and maximum link activity. Table 16. PCI Interface DC Specifications Parameter Condition 0 < V < V Networking Silicon — GD82559ER Typical Units Notes 4.75 5.25 = 3.3 V) and average link activity. Units Notes 0.475V...
  • Page 80 GD82559ER — Networking Silicon Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance CLKP IDSEL Pin Capacitance IDSEL Pin Inductance PINP NOTES: 1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buffer must consume its minimum current.
  • Page 81 = 3.3 V). Table 20. 10BASE-T Voltage/Current Characteristics Condition 10 MHz 5 MHz 10 MHz ±585 5 MHz 10 MHz RL = 100 RBIAS10 = 549 Networking Silicon — GD82559ER ±100 1.00 1.05 Icct100 21mA Typical Units Notes ±440 ±3100 ±440...

  • Page 82: Ac Specifications

    GD82559ER — Networking Silicon 10.3 AC Specifications Symbol Parameter Switching Current High OH(AC) (Test Point) Switching Current Low OL(AC) (Test Point) Low Clamp Current High Clamp Current PCI Output Rise slew Slew Rate PCI Output Fall slew Slew Rate NOTES: 1.

  • Page 83: Timing Specifications

    CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate Table 23. X1 Clock Specifications Parameter X1 Duty Cycle X1 Period Networking Silicon — GD82559ER shows the clock waveform and required 0.4V p-to-p (minimum) Units Notes V/ns Figure...

  • Page 84: Timing Parameters

    GD82559ER — Networking Silicon 10.4.2 Timing Parameters 10.4.2.1 Measurement and Test Conditions Figure Figure 28, and done. The component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. The design must guarantee that minimum timings are also met with maximum clock slew rate (fastest edge) and voltage swing.
  • Page 85 Input Hold Time from CLK Reset Active Time After Power Stable PCI Reset Active Time After CLK Stable Reset Active to Output Float Delay Figure Figure Networking Silicon — GD82559ER 0.325V Min Delay 0.475V Max Delay 0.475V Min Delay 0.325V Max Delay 0.4V...
  • Page 86 GD82559ER — Networking Silicon Symbol flrwc flacc flce floe fldf flas flah flcs flch flds fldh flwp flwph Mioha Miohi NOTES: 1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150 timings. 2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150 timings.
  • Page 87 Delay from EECS High to EESK High Delay from EESK Low to EECS Low Setup Time of EEDI to EESK Hold Time of EEDI after EESK EECS Low Time Networking Silicon — GD82559ER T 3 9 Data In Table 27 Units...
  • Page 88 GD82559ER — Networking Silicon E E C S F L A 1 5 E E S K F L A 1 3 E E D I 10.4.2.5 PHY Timings Symbol nlp_wid nlp_per Normal Link Pulse Symbol flp_wid flp_clk_clk flp_clk_dat flp_bur_num...
  • Page 89 Fast Link Pulse FLP Bursts Symbol Datasheet Networking Silicon — GD82559ER Clock Pulse Data Pulse Figure 32. Auto-Negotiation FLP Timings Table 30. 100Base-TX Transmitter AC Specification Parameter Condition TDP/TDN Differential HLS Data Output Peak Jitter Clock Pulse Units 1400...
  • Page 90 GD82559ER — Networking Silicon Datasheet...

  • Page 91: Package And Pinout Information

    Package and Pinout Information 12.1 Package Information The GD82559ER is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in Figure 24. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local Intel sales office.

  • Page 92: Pinout Information

    GD82559ER — Networking Silicon 12.2 Pinout Information 12.2.1 GD82559ER Pin Assignments Table 15. GD82559ER Pin Assignments Name Name SERR# IDSEL AD25 AD30 TEST AD22 AD23 AD24 AD26 VSSPP AD31 SPEEDLED RBIAS100 RBIAS10 AD21 RST# C/BE3# AD29 CLKRUN# VSSPT ACTLED AD18...
  • Page 93 FLA15/EESK FLA14/EEDO FLA13/EEDI Datasheet Table 15. GD82559ER Pin Assignments Name Name STOP# INTA# FLD5 FLD4 PERR# FLA0 FLD7 AD16 VSSPP FLA2 AD14 AD15 FLA4 FLA3 AD11 AD12 C/BE0# FLOE# FLA12 FLA7 FLA6 VSSPP AD10 FLA10 FLA8 EECS VSSPL FLA9 Networking Silicon — GD82559ER...

  • Page 94: Gd82559Er Ball Grid Array Diagram

    A D 3 A D 2 E E C S V S S P L Figure 25. GD82559ER Ball Grid Array Diagram A L T R S T V C C P T L I L E D T E S T...

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