Block Diagram - Marantz CD5004 Service Manual

BLOCK DIAGRAM

u-COM
20Mhz
26 28 57 58 59 61 65 67
SIO/UART 900/L1 CPU
(SIO0)
SIO/UART
XWA
(SIO1) W
XBC
B
SIO/UART XDE
D
(SIO2) XHL
H
XIX
IX
XIY
I2C 1Y
(SBIO) XIZ
IZ
XSP
SP
I2C
(SBI1) 32bit
8bit TIMER
(TMRA0)
P C
8bit TIMER
(TMRA1)
8bit TIMER
WATCH-DOG TIMER
(TMRA2)
8bit TIMER
(TMRA3)
Clock Timer
8bit TIMER
(TMRA4)
8bit TIMER
(TMRA5) R A M
8 K B R A M
16Bit TIMER
(TMRB0)
16Bit TIMER
(TMRB1)
R A M
16Bit TIMER
(TMRB2)
FLASH ROM 128KByte
16Bit TIMER
(TMRB3)
16Bit TIMER
ROM Correction
(TMRB4)
89
88
85
41 86
9 76 87 20 19 18 68 35 31 32
ST+5V
RS/REMOTE_IN
RS/REMOTE_IN
WELCOME
VP FST+5V
1 3
2
1 3
2
MAIN TRANS
VOUT
VIN
1 2
3 4
SUB TRANS
UPDATE PORT
SRAM
21 22 33
MEMORY ARRAY
256X 1024
DECODER
A0-A14
High-speed
SRAM_WE
Oscillator
4
SRAM_OE
A
5 I/O
SRAM_CE COLUMN I/O
C LOW-speed DATA
6
Oscillator ADDRESS PORT
E I/O1-I/O7 CIRCUIT
44~
L DATA PORT
9~
MODE
CONTROLLER
CE1
CONTROL
OE
CIRCUIT
INTERRUPT
WE
CONTROLLER
F
INTERRUPT
CONTROLLER
CD-BUS2
52
CD-BUS3
DATA BUS
53
CD-BUCK
ADDRESS BUS
54
CD-CCE
55
Memory
Controller
(blocks)
P O R T
CD-RST
56
1 0 - B I T
1 6 C H
A D
PLL_SCL
92
EEPROM
90
PLL_SDA
ST+5V ST+5V
RST
71 75 78 79 80 81 38 30
4 OUT VDD 5
3 2
NC VSS
1
DSP POWER
VDD
REMO
CLOCK(PLL+VCO)
FVDD FL+/-
+3.3VCL
+3.3V
PWR_MUTE
AUDIO-
AUDIO+
B+
+8V
3 1 VDD
2
VP
+8V +8V
IN
AUDIO+ 1
FL+
FL-
ST+5V
DSP_MCK
23
TC94A70FG
CD DSP
CD-RF
CD-RF
IN
Amp
VCC
GND
ST+5V
40
41 Audio
42
DAC
43
Analog
(Audio Out) Post
37
Filter
3.3V 1.5V
61 62 63 64
3 1 +P1.5V
2
3 1 +3.3V
3.3VDA
2
CDCE913
IN OUT
VCXO
1 3 +1.8V
16.9344 MHz
XO
GND LVCMOS
2
PLL
with SSC
EEPROM
PLL_SCL Programming
and
PLL_SDA Control Register
+1.8V +3.3VCL
DAC_MCK
DAC (CS4392)
DAC_RST
ANALOG
VOLUME
Control
FILTER DAC FILTER
SDATA
SERIAL INTERPOLATION
MIXER
SCLK PORT
INTERPOLATION ANALOG
LRCK
VOLUME
FILTER FILTER
Control DAC
NC
MODE
NC Selector EXTERNAL
Reference
Mute Control
NC (DAC_SDA) Control
Port
NC (DAC_SCL)
CMOUT FILT+
+3.3VA +5VA
OUT IN OUT
+3.3VA
3 1 3
GND GND
2 2
+5VA
33
13 12 10 9
E
100
F
98
Servo
Servo 97 B
96 D
ADC
Processor 95 A
C
94
CDP
Servo
MDI
92
DSP
DAC LDO
91
24-Bit
Peripheral
DSP
I/F
1 Mbit
PLL/VCO
SRAM
+VREF 3.3VDA +3.3V +P1.5V
VDD
DAC_MCK DSP_MCK
LV
CMOS
Divider
TC7WHU04FU
and
LV
Output
CMOS
Control
LV +3.3VCL
CMOS
AOUTA+
LPF (OP Amp IC)
AOUTA-
+
AOUTB+
Tr.Bu er
AOUTB-
A_MUTE
+12V -12V
B_MUTE
+12V
HEADPHONE A
OUTPUT
B
-12V
OP/SW
CL/SW
DRIVE I.C LIMIT SW
COM
35 LOADING+
M
RL5
34
33 LOADING-
SPINDLE MOTOR
SPINDLE+
RL4 M
SPINDLE-
SLED+ M
RL3
SLED MOTOR
SLED-
TR+/-
SPINDLE-
RL1
SPINDLE+
FC+/- SLED-
SLED+
RL2
+VREF +8V
E
C D
B A
F
+RF3.3V
+VREF
OPTICAL OUT
COAXIAL OUT
ST+5V
INTERNAL L
EXTERNAL H
SYS DETECT
SYS_DETECT
RS_REMOTE_IN
REMO
BUS IN/OUT
FLUSHER IN(U Ver ONLY)
UPDATE
UPDATE PORT
RST/ST+5V/GND
L
ANALOG L
F_MUTE
A_MUTE
P_MUTE
R
ANALOG R
F_MUTE
B_MUTE
P_MUTE