Harman Kardon AVR 3600 Service Manual page 121

7 x 80w 7.1 channel a/v receiver
Hide thumbs Also See for AVR 3600:
Table of Contents

Advertisement

AVR3600
ESMT
1. FEATURES
Single supply voltage 2.7V-3.6V
Fast access time: 70/90 ns
4,194,304x8 / 2,097,152x16 switchable by BYTE pin
Compatible with JEDEC standard
- Pin-out, packages and software commands compatible with
single-power supply Flash
Low power consumption
- 20mA typical active current
- 25uA typical standby current 
100,000 program/erase cycles typically
20 Years Data Retention 
Command register architecture
- Byte Word Programming (9μs/11μs typical)
- Byte Mode : eight 8KB, sixty three 64KB sectors.
- Word Mode : eight 4K word, sixty-three 32 K word sectors.
Auto Erase (chip & sector) and Auto Program
- Any combination of sectors can be erased concurrently;
Chip erase also provided.
- Automatically program and verify data at specified address
Erase Suspend/Erase Resume
- Suspend or Resume erasing sectors to allow the
read/program in another sector
Secured Silicon Sector
- 128word sector for permanent, secure identification through
an 8- word random Electronic Serial Number
- May be programmed and locked at the factory or by the
-
customer
-
- Accessible through a command sequence.
2. ORDERING INFORMATION
Part No
Boot
F49L320UA-70TG
Upper
F49L320BA-70TG
Bottom
3. GENERAL DESCRIPTION
The F49L320UA/F49L320BA is a 32 Megabit, 3V only CMOS
Flash memory device organized as 4M bytes of 8 bits or 2M
words of 16bits. This device is packaged in standard 48-pin
TSOP. It is designed to be programmed and erased both in
system and can in standard EPROM programmers.
With
access
times
F49L320UA/F49L320BA allows the operation of high-speed
microprocessors. The device has separate chip enable CE , write
enable
, and output enable OE controls. ESMT's memory
WE
devices reliably store memory data even after 100,000 program
and erase cycles.
The F49L320UA/F49L320BA is entirely pin and command set
compatible with the JEDEC standard for 32 Megabit Flash
memory devices. Commands are written to
The F49L320UA/F49L320BA features a sector erase architecture.
The device array is divided into eight 8KB, sixty-three 64KB for
Elite Semiconductor Memory Technology Inc.
Preliminary
Speed Package Comments
70 ns
TSOPI
70 ns
TSOPI
of
70
ns
and
90
3V Only CMOS Flash Memory
Ready/Busy (RY/ BY )
- RY/
output pin for detection of program or erase operation
BY
completion
End of program or erase detection
- Data polling
- Toggle bits
Hardware reset
- Hardware pin ( ESET
the read mode
Sector Protection /Unprotection
- Hardware Protect/Unprotect any combination of sectors from
a program or erase operation.
Low V
Write inhibit is equal to or less than 2.0V
CC
Boot Sector Architecture
- U = Upper Boot Block
- B = Bottom Boot Block
Packages available:
- 48-pin TSOPI
- All Pb-free products are RoHS-Compliant
CFI (Common Flash Interface) complaint
- Provides device-specific information to the system, allowing
host software to easily reconfigure to different Flash devices.
Part No
Pb-free
F49L320UA-90TG
Pb-free
F49L320BA-90TG
byte mode. The device memory array is divided into eight 4K
word, sixty-three 32K word sectors for word mode. Sectors can
be erased individually or in groups without affecting the data in
other sectors. Multiple-sector erase and whole chip erase
capabilities provide the flexibility to revise the data in the
device.
ns,
the
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory. This can be achieved in-system or via programming
equipment.
A low V
detector inhibits write operations on loss of power.
CC
End of program or erase is detected by the Ready/Busy status
pin, Data Polling of DQ7, or by the Toggle Bit I feature on DQ6.
Once the program or erase cycle has been successfully
completed, the device internally resets to the Read mode. The
command register using standard microprocessor write
timings.
121
F49L320UA/F49L320BA
32 Mbit (4M x 8/2M x 16)
) resets the internal state machine to
R
Boot
Speed
Package
Upper
90 ns
TSOPI
Bottom
90 ns
TSOPI
Publication Date : Jan. 2008
Revision: 0.4
harman/kardon
Comments
Pb-free
Pb-free
1/54

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

Avr 2600

Table of Contents