Power Block Diagram - Panasonic Lumix DMC-FZ200P Service Manual

11.5. Power Block Diagram

POWER BLOCK DIAGRAM
FLASH P.C.B.
CL9011
P8001
F8002
PP8001 PS9001
BAT+ 1
11-14
TO
PP8001 PS9001
BATTERY BAT THERMO 2
5
CATCHER
CL9012
NC
3
PP8501 PS9001
BAT- 4
1,2,19,20
IC9101
(SYSTEM IC)
CL9008
SUB P.C.B.
(BACKUP)
FP9302 FP9006
27 BATT
14 36
B9301
BACK BATT
TOP OPERATION UNIT
POWER SW
CL9004
(POWER ON L)
ON
FP9002
87
14
RL9111
OFF
54
IC6001
(VENUS ENGINE)
(POWER SW ON)
CL6014
GPIO42 AB21
(POWER ON H)
GPIO20 AC18
(SYS RESET)
RSTB AC12
(BATT THERMO)
AD0 IN1 B11
(SW UNREG)
AD0 IN0 A11
(PW SD3018V)
VDD SD Y20
VDD SD AA22 IC6401
QR6402
(REGULATOR)
1 4
VOUT VIN
2 VSS VCNT 3
(1R8V ON)
GPIO76
W4
(3R0V ON)
GPIO77 W3
4 5
Q6401
3 2
(SD POWER ON )
QR6401
GPIO56 AF10
(S I2C SCL)
GPIO45 AB18
(S I2C SDA)
GPIO47 AB16
(LCD BLT)
GPIO31 AD15
PW BL MINUS
(To FP9003-7)
PW BL PLUS
(To FP9003-6)
(UNREG)
(BAT THERMO)
IC1001
(7CH SW REGULATOR)
Q9101
VO1
4
VO2
5
UNREG 34
VO3
CL1001
6
POWER CTL SW 35
SERIAL I/F
VO4
POWER SW ON L 7
POWER SW ON H
VO5
POWER ON H RESETOUT
8
84 85
VO6
9
CL6402
SERIAL I/F
CL9102
INV7
32
SERIAL I/F
6
CL6401
1
CTL SEQ3
VDD
13
(To P6401-4A,4B)
CTL SEQ2
14
CTL SEQ1
16
CTL1234
17
SCL
18
SDA
19
CL1072
CL1071
CL1070
Q1071
61
62
HVREG
DRIVER 63
CH1
STEP DOWN DC/DC 64
VREGD
(Current mode)
DRIVER 59
ERROR AMP1
SERIAL I/F
60
57
HVREG
DRIVER
CH2
STEP DOWN DC/DC 58
VREGD
(Current mode)
DRIVER
ERROR AMP2
SERIAL I/F
56
54
HVREG
Vo3SEL
DRIVER
CH3
STEP DOWN DC/DC 55
VREGD
(Current mode)
DRIVER 52
ERROR AMP3
53
49
HVREG
DRIVER
50
CH4
51
STEP DOWN DC/DC
VREGD
(Current mode)
DRIVER 48
ERROR AMP4
SERIAL I/F
44
45
HVREG
DRIVER 46
CH5
47
STEP DOWN DC/DC
VREGD
(Current mode)
DRIVER 42
ERROR AMP5
SERIAL I/F 43
38
HVREG
DRIVER 39
CH6
STEP DOWN DC/DC 40
VREGD
(Current mode)
41
DRIVER
ERROR AMP6
36
37
35
VREGD
CH7 DRIVER
34
STEP UP DC/DC
ERROR AMP7
(Current mode)
0.3V
33
SHUTDOWN
SS TIMER
OVPCOMP
PROTECTION
SCP6
UVLO
TIMER
30
LDO
31
22
SCP
TIMER
10
28
VREGD2
25
23
C P SW
SCPLDO
2
TIMER CP
DRIVER
VREGD
ON/OFF
3
LOGIC
CP SW 24
1
VREGA
SERIAL
I/F OSC
20
VREGD
12 21 26 27
29
SEQ
RT VREGD2 VREGA VREGD
56
Hx1
Hx1
Lx1
Lx1
PGND1
PGND1
Hx2
Lx2
PGND2
Hx3
Lx3
IC1042
PGND3
(DC/DC CONVERTER)
PGND3
Hx4
Hx4
PHASE
CONPENSATION
Lx4
PGND4 ERROR
CURR. LIMIT
PWM
AMP
COMP.
Hx5
+
LOGIC
Hx5
Lx5
VSHORT
Lx5
VREF WITH
PWM/PFM
PGND5
SOFT START,
SELECTOR
CE
PGND5
Hx6
RAMP WAVE
CE/MODE CE/MODE
CONTROL GENERATOR
Hx6 4
LOGIC
Lx6
UVLO
Lx6 COMP.
VIN
6
PGND6
PGND6
Lx7
PGND7
IC1043
VO7
(REGULATOR)
4
VIN VOUT 1
3 VSS 2
CE
VINREG
VINREG
REGOUT
VDD
VREGD2IN
HVREG
CPLUS
VBAT
VBAT
CMINUS
VCC
IC1061
GND
(REGULATOR)
1 CE VIN 4
2 VSS VOUT 3
CL1050
PW 5.2V
CL1010
PW D1.2V
CL1020
PW D3.0V
IC1021
(REGULATOR) CL1021
4
VIN VOUT 1 PW SE2.8V
3 CE VSS 2
CL1030
PW DM1.2V
CL1040
PW AF3.4V
IC1041
(REGULATOR)
1 CNT VDD 4
CL1041
2 GND VOUT 3 PW A3.1V
VOUT
3
CURR. F.B.
SYNC.
LX
BUFFER
1
DRIVE
CE/
OSC
VSS
2
VSS
UVLO
5
CL1042
PW EVF1.8V
IC1044
(REGULATOR) CL1043
4 VIN VOUT 1 PW SE1.8V
3 2
CE VSS
IC1045
(REGULATOR)
1 4
CE VDD
CL1044
2 VSS VOUT 3
PW D1.8V
CL1060
PW SE1.2V
CL1080
PW HDMI5.0V
DMC-FZ200 POWER BLOCK DIAGRAM