MSI MS-7793 Manual page 48

MS-7793 Manboard
▶ tCL
Controls CAS latency whch determnes the tmng delay (n clock cycles) of startng
a read command after recevng data.
▶ tRCD
Determnes the tmng of the transton from RAS (row address strobe) to CAS
(column address strobe). The less clock cycles, the faster the DRAM performance.
▶ tRP
Controls number of cycles for RAS (row address strobe) to be allowed to pre-charge.
If nsufficent tme s allowed for RAS to accumulate before DRAM refresh, the DRAM
may fal to retan data. Ths tem apples only when synchronous DRAM s nstalled
n the system.
▶ tRAS
Determnes the tme RAS (row address strobe) takes to read from and wrte to
memory cell.
▶ tRTP
Ths tem s used to adjust the tme nterval between a read and a precharge
command.
▶ tRC
The row cycle tme determnes the mnmum number of clock cycles a memory row
takes to complete a full cycle, from row actvaton up to the prechargng of the actve
row.
▶ tWR
Mnmum tme nterval between end of wrte data burst and the start of a precharge
command. Allows sense amplfiers to restore data to cells.
▶ tRRD
Specfies the actve-to-actve delay of dfferent banks.
▶ tWTR
Mnmum tme nterval between the end of wrte data burst and the start of a
columnread command. It allows I/O gatng to overdrve sense amplfiers before read
command starts.
▶ tRFC0/ 1
These settngs determne the tme RFC0/1 takes to read from and wrte to a memory
cell.
▶ Advanced Channel 1/ 2 Tmng Configuraton
Press <Enter> to enter the sub-menu. And you can set the advanced memory tmng
for each channel.
▶ CPU Core Vdroop Offset Control
Ths tem s used to select the CPU core Vdroop offset control mode.
▶ CPU NB Vdroop Offset Control
Ths tem s used to select the CPU-NB Vdroop offset control mode.
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