Yamaha GX-505 Service Manual page 50

A B C
GX-505/GX-505VCD
SCHEMATIC DIAGRAM (GX-505VCD VCD)
1
CD HEAD AMP
2
3
4.3
3.7
1.8
4
ACT
MOTOR
DRIVE
0
0
5.6
2.4
2.4
2.4 2.4
2.1 2.5
0 0 2.7
0 0
5.6
0 0
5
0 0
2.4 5.6
2.5 ~
2.5 ~
2.4
2.4
2.4
5.6 5.6
5.6
0
4.8
0
6
7
8
MOTOR DRIVE
9
VCD
10
63
D E F
3.2
4.9
0
0
4.3
2.4 4.8
2.4
1.3 0
2.4
~
4.8
1.9 0
4.8
0
0
0
0
4.8
~ 4.9
~
SPC & DAC
2.4
0 0
0
2.4 2.4 2.3
2.3 2.4
4.8 2.4
q
2.4
1.3
2.4
4.8
w
0
4.1
4.3
2.1
2.3
0
0
0 0
0
0
0
0
0
4.8
0
0
4.0
0
6.0 0
4.8
0 0
0
G H I
4.8 5.5
REGULATOR
REGULATOR
4.9 8.0
5.6 10.8
7.3
1.7
6.2
6.2
1.2
0 1.2
0
0
1.2 7.3
6.2
0
2.7
0
0
0
0
4.8
14
4.8 4.8
11 12
13 4.8
0
14
4.8 11 0
4.8 10
10
~ 9 4.8
8
4.8
10
0 9 ~
11
0 8 9 4.8
0
1 7
~ 0
2 3 ~
7
0
2.4
4.8 5
0 3
0
0 5
4.8
0
0
0
0
0
CD CPU
0
0
0
4.8
0
0
0
0
0
0
0
0
0
0
4.8 5 6 3 4
4.8
0
12.2
12.2
MUTING
8
0 2
0 0 3 8
0 3 0
1
0 2 1
-12.0
0
LPF
0
0
0
-12.0
6
0
0 5 0
0 0 5
7
0 6 4
7
4
-12.1
-12.1
Point q (Pin59 of IC5) Point w (Pin39 of IC8)
H : 0.1 µsec/div
V : 2V/div H : 50 nsec/div V : 2V/div
DC range 1 : 1 probe DC range 1 : 1 probe
0V
0V
J K
IC4 : AN8806SB
Digital Servo Head Amp
6 7 29
+
VCBA
PDAC
36 +
+
MAIN(1)
P68
VCBA
A-2
PDBD 35
+
+
PDFR 31
VCBA
PDF 34
+
+
VCBA
+
PDER
32
PDE 33 +
INPUT(1) +
P65
A-9
30 24
INPUT(2)
P65
D-8
INPUT(2)
P65
E-8
2.4
2
1
4.8
14
6 0 4.8
3 4
7
0
4.8
1
0
2
IC9, 12 : TC74HC125AF IC11 : TC74VHC14F
7
Quad 3 State Bus Buffers Hex Schmit Trigger Inverters
4.8
14
6 0
1C 1 Vcc
14 I1 1
4
0
1A 2 13 4C O1 2
1Y 3 12 4A I2 3
2C 4 11 4Y O2 4
2A 5 10 3C I3 5
2Y 6 9 3A O3 6
GND 7 8 3Y V SS 7
IC10 : TC74HC04AF IC13, 14 :
Hex Inverters Dual OP-Amp
OUT 1 1
1A 1 14 V DD
0 1 2 4.8
–IN 1 2
1Y 2 13 6A
+IN 3
2A 3 12 6Y 1
2Y 4 11 5A –V CC 4
3A 5 10 5Y
3Y 6 9 4A
CD(Lch)
V SS 7 8 4Y
IC2, 3 : TA8409S
Full Bridge Motor Driver
4.8
VCC VS
4.8 2 6
STAND-BY
CIRCUIT
-12.0
IN 1
9
IN 2 1
THERMAL
SHUTDOWN
CIRCUIT
5
GND
L M N
IC1 : M56748FP
4 Channel BTL Driver
27 28 8 9 10 17 11 12 19 STAND
TSD
BY
VREF-IN OP1 STAND BY
1 36
+ VREF-OUT 2 35 SS. GND
RF
EQ AGC
DETECT N. C. 3 STAND BY
34
OP1 OP1
ENV DETECT
GAIN 1 4 33 GAIN 4
C.SBDO 10K 10K 10K 10K
BDO 13
VCTL 1 (–) 5 32 VCTL 4 (–)
14 BDO
VM 1 (–) 6 31 VM 4 (–)
PA
15 C.SBRT PA
OFTR
+ VM 1 (+) 7 30 VM 4 (+)
16 OFTR
PA PA
8 29
+
VREF
20
9 28
GND GND
10 27
5 VCC
11 26
+
18 GND
PA PA
VM 2 (+) 12 25 VM 3 (+)
21 LD OFF PA PA
VM 2 (–) 13 24 VM 3 (–)
+ 10K 10K
+ + 2 LD VCTL 2 (–) 14 23 VCTL 3 (OUT)
+ OP1 OP1
GAIN 2 15 22 VCTL 3 (–)
N. C. 16 21 VCTL 3 (+)
25 26 23 22 1 4 3 OP1 10K VCC
VCC 17 20 VCC
OP1
REG 5V 18 19 REGBASE
10.8K 3.6K
VCD MODULE ( VZ150200)
CONNECTION TERMINAL SPECIFICATION
NO. TERMINAL I/O FUNCTION
1 A+3.3V +3.3V POWER SUPPLY FOR ANALOG VIDEO
2 CVOUT O COMPOSITE VIDEO OUT
3 COUT O C VIDEO OUTPUT (S)
4 YOUT O Y VIDEO OUTPUT (S)
5 VGND ANALOG VIDEO GROUND
6 VGND ANALOG VIDEO GROUND
7 R+5V DIGITAL +5V POWER SUPPLY
8 D+3.3V DIGITAL +3.3V POWER SUPPLY
9 D+3.3V DIGITAL +3.3V POWER SUPPLY
10 DGND DIGITAL GROUND
11 DGND DIGITAL GROUND
12 XCK I AUDIO EXTERNAL FREQUENCY CLOCK
13 EMPH O AUDIO EMPHASIS OUTPUT
14 DILRCK O AUDIO LEFT RIGHT CLOCK
15 HRDY O HOST DATA READY
16 DISCK O AUDIO BIT CLOCK
17 DIDATA O AUDIO DATA SERIAL BUS
18 HINT O HOST INTERRUPT
19 SBCK O SUBCODE CLOCK FOR CD-G
20 VRST I HARDWARE RESET (LOW ACTIVE)
21 HCK I HOST CLOCK
22 HDIO I/O HOST SERIAL DATA BUS
23 CDSCK I CD BIT CLOCK
24 CDDATA I CD DATA
25 CDLRCK I CD LEFT RIGHT CLOCK
26 IPFLG I CD DATA ERROR FLAG (C2P0)
27 HSEL I HOST ADDRESS/DATA SELECT
28 SUBC I SUBCODE DATA FOR CD-G
29 CLDCK I SUBCODE FRAME SYNC FOR CD-G
30 BLKCK I SUBCODE BLOCK SYNC FOR CD-G
NOTE: None of the components of the VCD module can be supplied
separately. Only a VCD module unit (VZ150200) is available.
14 V DD
13 I6
12 O6
11 I5
10 O5
2. SUBCODE INTERFACE
9 I4
8 O4
µ
PC4570G2
8 +V CC
7 OUT 2
+ – + –
6 –IN
2
5 +IN 2
3. AUDIO OUTPUT INTERFACE
4. HOST INTERFACE
HOST READ TIMING
VREF
8 VREF
CIRCUIT
7
OUT 1
3 OUT 2
HOST WRITE TIMING
* All voltage are measured with a 10M Ω /V DC electric volt meter.
* Components having special characteristics are marked Z and
must be replaced with parts having specifications equal to those
originally installed.
* Schematic diagram is subject to change without notice.
O