Audio Memory; Master Clock Generator; I/O; Seeprom - Lexicon MPX 110 Service Manual

MPX 110 Service Manual
activity on the ZD bus. So, the Z80 and the L3 have separate resets (ZRST/ and RESET/ respectively).
When the Z80 comes up in reset, it will have indeterminate data on the bus. The Z80 needs some clock
cycle while in reset to drive its data bus to hi-Z. This explains the need for circuitry U6 and U7, R32, and
C24 (4B7). It provides separate reset and clocks to the Z80 so it can set its data bus to hi-Z while in reset
and stay reset while the L3 comes out of reset and reads the configuration resistors.
R68, R76, and C67 form a reference network for the PLL. R73 and R74 provide weak pull-ups for
SP_MASTER/ and SPDIF_OUT respectively. R92 and R100 provide weak pull-downs for MUTE/ and
DE_EMPH/ respectively. These pull-down components ensure that these signals default to their active
states during power up. Resistors R69, R70, R71, and R77 provide RFI protection by slowing down the
edge rates of LEX_FS/, D/A_DATA, LEX_64FS/, and LEX_256FS respectively. R72 is a provision for
further RFI protection. Currently all that is required is for this component to be a 0-ohm resistor. R75
provides a DC coupled power source to the internal PLL on the Lexichip3. C68 and C69 de-couple this
supply line.

AUDIO MEMORY

The audio memory for the Lexichip3 is provided by 1Mx16 DRAM (U10). However, the MPX110 only uses 8
of the available 16 data bits, with the most significant byte pulled up by RP5-RP6 Effectively this DRAM is
being used as a 1Mx8 device. The address bus and memory control signals provided by the Lexichip3 are
series terminated by resistors R93 through R98 and R101 through R107. This is done to provide RFI
protection. Since the most active signals on this bus are LEX_A0 and LEX_A1, these are the ones that will
cause the most emission, therefore R93 and R101 are set to 180 ohms; this value effectively slows down
the edge rates of these two signals. The remaining bus signals (LEX_A[2:9]) are less active and therefore
do not require edge rate reduction; R94, R96 through R98, R102, R105 and R106 are set to 0 ohms.
Control signals CAS/, RAS/ and WE/ require edge rate reduction due to their high level of activity.
Therefore, R95, R103, and R104 are 180 ohms.

MASTER CLOCK GENERATOR

Y1, C76, C77, and R91 comprise the master clock generator. Signal LEX_256FS is equal to the frequency
generated here (11.2896MHz). Pins 74 and 75 on the Lexichip3 are essentially the output and input of a
CMOS buffer, respectively.

I/O

The L3 is used in many Lexicon products and provides most of the I/O needed by embedded systems like
the MPX-110. Looking over the L3 you will find pins designated "PIOA" and "PIOB". These are
programmable pins for I/O. For example: pin 95, "PIOB_2" controls "SWITCH ROW0" and pin 31, "PIOA_5"
controls "SWITCH ROW1". These I/O pins latch the state of the "TAP", "BYPASS", and "STORE" switches
(7/B2). The Z80 sets up the L3 I/O direction register and reads or writes to the port register in order to get or
provide peripheral device information. The L3 registers are addressed with signals ZA[15:0], read or written
to with ZD[7:0] and controlled by ZCTRL.
The Z80 also uses the L3 to store system parameters when the MPX-110 is shutdown. Parameters like,
Global tempo and the tap status. The serial eeprom, SEEPROM (U12) is clocked by "PIOB_5" pin96 and
data stored or retrieved by "PIOB_4" pin 98.

SEEPROM

Non-volatile data storage is incorporated with a 2 wire serial/I2C 24C32 (32K bit). This serial EEPROM
(U12) uses a two-wire bus protocol. U12, pin 5 is the serial address/data input/output, this is a bi-directional
pin used to transfer addresses and data into and out of the device. U12, pin 6 is the serial clock input used
to synchronize the data transfer to and from the device.
Currently pins 98 and 96 of Lexichip 3 are configured as PIOB (7) and PIOB (4). PIOB (7)(pin 96) is used
to generate the serial clock and PIOB (4)(pin 98) is the bi-directional address/data for the EEPROM.
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