Diagnostic Failures; Rom Checksum Test (1); Sram Test (2) - Lexicon MPX 110 Service Manual

MPX 110 Service Manual

DIAGNOSTIC FAILURES

When a failure is encountered during the test sequence:
- The test code is displayed on the Binary LED's (Ref. Table 1).
- The Clip (red) Headroom LED's are turned on to indicate a failure has occurred.
- The unit stops executing the Power On Diagnostic test sequence.
- The audio outputs are muted, and the unit will not become operational.
If the BYPASS button is pressed after a failure has occurred, the MPX 110 will attempt to continue on with
the next test of the Power On Diagnostic test sequence, and the MPX 110 will attempt to do this every time
the BYPASS button is pressed.
If the STORE button is pressed after a failure has occurred, the MPX 110 will enter the Extended
Diagnostics mode.
If the TAP button is pressed after a failure has occurred, the MPX 110 will run the test continuously.
The following diagram describes the Binary LED's:
Edit Bypass
O O
MSB
LED Off = O (0)
LED On = l (1)
This figure shows an example of the Binary LED's Failure Code 3 (0011). This code indicates that the
Lexichip3 WCS Test has failed.

ROM CHECKSUM TEST (1)

The ROM checksum, is a byte size value that is stored in the last location of Bank 0 . The test adds the
contents of the entire ROM including the Checksum byte. The result should equal zero (8 bit value).
Before the test is executed, a test code will be put out on the Binary LED's. The code is:
Edit Bypass
O O
MSB
If a failure occurs, the Clip (red) headroom LED's will be turned on in addition to the binary code, and the
CPU will attempt to continuously loop the test for troubleshooting purposes.
If the BYPASS button is pressed, the failure is ignored and the next test will be executed.

SRAM TEST (2)

The SRAM Test performed during the Power On Diagnostics is a destructive test. The entire contents of the
SRAM is tested by first writing 00 hex (00000000 binary) to all of the memory locations, and then verified by
reading back all of the memory locations. This write/read sequence is also performed using the following
5-2
Store Tap
l l
LSB
Figure 1.
Store Tap
l
O
LSB