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3. TECHNICAL BRIEF
3.6 Digital Main Processor
The AD6522 is an ADI designed processor.
Figure 3-6. Top level block diagram of the AD6522 internal architecture.
BUS Arbitration Subsystem
It is to work as a cross point for data accesses between the three main busses. EBUS is for external
accesses, primarily from Flash memory for code and data. RBUS is for internal RAM access. PBUS
is for access to internal peripheral modules such as UART, RTC or SIM. In addition to the three
main system busses, it has SBUS, IOBUS and DMABUS.
DSP subsystem
It consists of ADI DSP, Viterbi coprocessor, Ciphering unit and a cache memory/controller system.
The DSP can run at a maximum clock frequency of 78 MHz at 2.45 V. The Viterbi and ciphering
accelerators enable a very efficient implementation of the channel equalization, encryption and
decryption tasks.
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