Advanced Chipset Features - MSI G52-72381X1 User Giude

Advanced Chipset Features

Configure DRAM Timing by SPD
The system board designer must select the proper value for this field, according to
the specifications of the installed DRAM chips. W hen Disabled, you can select the
DRAM timing type.
DRAM CAS# Latency
W hen the Configure DRAM Timing by SPD sets to [Disabled], the field is
adjustable.This controls the CAS latency, which determines the timing delay (in
clock cycles) before SDRAM starts a read command after receiving it.
DRAM RAS# to CAS# Delay
W hen the Configure DRAM Timing by SPD sets to [Disabled], the field is
adjustable. W hen DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the transition
from RAS (row address strobe) to CAS (column address strobe). The less the
clock cycles, the faster the DRAM performance.
DRAM RAS# Precharge
W hen the Configure DRAM Timing by SPD sets to [Disabled], the field is
adjustable. This item controls the number of cycles for Row Address Strobe
(RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refreshing may be incomplete and
DRAM may fail to retain data. This item applies only when synchronous DRAM is
installed in the system.
BIOS Setup
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