Advanced Chipset Features - MSI MS-6330 Technical Manual

Chapter 3

Advanced Chipset Features

CMOS Setup Utility - Copyright (C) 1984-2000 Award Software
Bank Interleave
DRAM Timing by SPD
x
SDRAM CAS Latency
Memory Hole
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP-4X Mode
AGP Driving Control
x
AGP Driving Value
OnChip USB
USB Keyboard Support
USB Mouse Support
OnChip Sound
OnChip Modem
CPU to PCI Write Buffer
PCI Dynamic Bursting
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
- Next Page -
PCI Master 0 WS Write
PCI Delay Transaction
PCI#2 Access #1 Retry
AGP Master 1 WS Write
AGP Master 1 WS Read
Memory Parity/ECC Check
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.
Bank Interleave
The field is used to enable or disable memory bank interleave feature.
Settings: Enabled and Disabled.
DRAM Timing by SPD
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to Yes enables SDRAM
Advanced Chipset Features
Enabled
Yes
Auto
Disabled
Enabled
Disabled
Disabled
Disabled
64M
Enabled
Auto
DA
Enabled
Disabled
Disabled
Auto
Auto
Enabled
Enabled
F6:Fail-Safe Defaults
Enabled
Enabled
Disabled
Enabled
Enabled
Disabled
F6:Fail-Safe Defaults
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Item Help
Menu Level 8
F7:Optimized Defaults
Item Help
Menu Level 8
F7:Optimized Defaults