Abit KV-82 User Manual page 31

BIOS Setup 3-9
DRAM Timing Selectable:
This option selects the method of DRAM timing. When set to [By SPD], the BIOS will read the DRAM
module SPD data automatically. When set to [Manual], the following sub-items will be available to make
adjustments.
LDT & PCI Bus Control:
Click <Enter> key to enter its submenu:
Upstream/Downstream LDT Bus Width:
This item allows you to select LDT Bus Width.
LDT Bus Frequency:
This item allows you to select LDT Bus Frequency.
PCI1 Master 0 WS Write:
Two options are available: Enabled or Disabled. The default setting is Enabled. When Enabled, writes to
the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is
set to Disabled, the system will wait one state before data is written to the PCI bus.
PCI1/PCI2 Post Write:
Two options are available: Enabled or Disabled. The default is Enabled, When Enable, data transmission
from CPU to PCI bus are buffered and compensate for the different speed between CPU and PCI bus. If it
is set to Disabled, data transmissions are not buffered and CPU must wait until the data transmission is
complete and then start another transmission cycle.
PCI Delay Transaction:
Two options are available: Disabled or Enabled. The default setting is Enabled. The chipset has an
embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support
compliance with PCI specification version 2.2.
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