Denon DHT-391XP Service Manual page 84

Location Mnemonic
87 AP0_OUT
88 AP1_OUT
89 AP2_OUT
90 AP3_OUT
91 AP4_OUT
92 DGND
93 DVDD
94 AP5_OUT
95 SCLK_OUT
96 MCLK_OUT
97 RESETB
98 PWRDNB
99 PGND
100 PVDD
101 XTAL
102 XTAL1
103 PVDD
104 PGND
105 HP_CTRLA
106 5V_DETA
107 RTERM
108 DDCA_SDA
109 DDCA_SCL
110 CVDD
111 CGND
Type
Digital Output Audio output port 0.
Digital Output Audio output port 1.
Digital Output Audio output port 2.
Digital Output Audio output port 3.
Digital Output Audio output port 4.
Ground Ground for DVDD
Power Digital supply voltage (1.8 V)
Digital Output Audio output port 5.
Digital Output Audio serial clock output.
Digital Output Audio master clock output.
Digital Input System reset input. Active low. A minimum
low reset pulse width of 5 ms is required to
reset the ADV7622 circuitry.
Digital Input Active low power-down pin. This pin
should be used as a system detect when the
internal EDID is powered from the 5V
signal from the HDMI port when connected
to active equipment. Pin pulled down
internally.
Ground Ground for PVDD
Power PLL supply voltage
Miscellaneous Input pin for 28.63636 MHz crystal or an
Analog external 1.8 V 28.63636 MHz clock
oscillator source to clock the ADV7622.
The following crystal frequencies are also
supported: 24.576 MHz and 27 MHz.
Miscellaneous Crystal output pin. This pin should be left
Analog floating if a clock oscillator is used.
Power PLL supply voltage
Ground PVDD Ground
Digital Output Hot Plug Detect for port A.
Digital Input 5 V detect pin for port A in the HDMI
interface.
Miscellaneous Sets internal termination resistance. A 500
Analog Ω resistor between this pin and GND
should be used.
Digital I/O HDCP slave serial data port A.
DDCD_SDA is a 3.3 V input/output that is
5 V tolerant.
Digital Input HDCP slave serial clock port A.
DDCD_SCL is a 3.3 V input that is 5 V
tolerant.
Power Receiver comparator supply voltage (1.8V)
Ground TVDD and CVDD Ground
84
Description