Texas Instruments TAS3002 Data Manual
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Texas Instruments TAS3002 Data Manual

Texas Instruments TAS3002 Data Manual

Digital audio processor with codec
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TAS3002
Digital Audio Processor With Codec
Data
Manual
2001
Digital Audio: Digital Speakers
SLAS307B

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Summary of Contents for Texas Instruments TAS3002

  • Page 1 TAS3002 Digital Audio Processor With Codec Data Manual 2001 Digital Audio: Digital Speakers SLAS307B...
  • Page 2 ) may be set to 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface formats are listed and described in Section 2.1. The TAS3002 device uses a system clock generated by the internal phase-locked loop (PLL). The reference clock for the PLL is provided by an external master clock (MCLK) of 256 f...

  • Page 3: Functional Block Diagram

    Can have crystal input to replace MCLK. Crystal input frequency is 256 f Six GPI terminals for volume, bass, treble up/down control, mute, and selection of equalization filters 1.3 Functional Block Diagram Figure 1−1 is a block diagram showing the major functions of the TAS3002. 1−2...
  • Page 4 AINLP LINB AINLM VCOM ALLPASS INPA AOUTL GPI5 AOUTR GPI4 GPI3 24-Bit GPI2 Stereo DAC GPI1 GPI0 SDOUT2 32-Bit Audio Signal Processor SDOUT1 32-Bit Audio Signal PWR_DN Processor RESET TEST SDATA OSC/CLK Control Select Figure 1−1. TAS3002 Block Diagram 1−3...

  • Page 5: Terminal Assignments

    14 15 17 18 19 20 21 22 23 24 Figure 1−2. TAS3002 Terminal Assignments 1.5 Terminal Functions Table 1−1 lists the terminals in alphanumeric order by signal name, along with the terminal number, terminal type, and a description of the terminal function.
  • Page 6 No connection; Can be used as a printed circuit board routing channel PWR_DN Logic high places the TAS3002 device in power-down mode RESET Logic low resets the TAS3002 device to the initial state RINA Right channel analog input 1 RINB...
  • Page 7 1−6...
  • Page 8 MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart. If the LRCLK phase changes by more than 10 cycles of MCLK, the codec automatically resets. The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I S, right justified, and left justified.

  • Page 9: Digital Output Modes

    2.2 Digital Output Modes The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3. 2.2.1 MSB-First, Right-Justified, Serial-Interface Format The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−1 shows the following characteristics of this protocol: Left channel is transmitted when LRCLK is high.
  • Page 10 2.2.2 S Serial-Interface Format The normal output mode for the I S serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−2 shows the following characteristics of this protocol: Left channel is transmitted when LRCLK is low. SDIN is sampled with the rising edge of SCLK. SDOUT is transmitted on the falling edge of SCLK.
  • Page 11 2.2.3 MSB-Left-Justified, Serial-Interface Format The normal output mode for the MSB-left-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−3 shows the following characteristics of this protocol: Left channel is transmitted when LRCLK is high. The SDIN data is justified to the leading edge of the LRCLK. The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.

  • Page 12: Switching Characteristics

    2.3 Switching Characteristics PARAMETER UNIT t c(SCLK) SCLK cycle time 325.5 t d(SLR) SCLK rising to LRCLK edge t d(SDOUT) SDOUT valid from SCLK falling edge (see Note 1) (1/256 f S ) + 10 t su(SDIN) SDIN setup before SCLK rising edge t h(SDIN) SDIN hold after SCLK rising edge f (LRCLK)
  • Page 13 2−6...

  • Page 14: Analog Input/Output

    3 Analog Input/Output The TAS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A or B analog input is accomplished by setting a bit in the analog control register (ACR) by an I C command.
  • Page 15 3.2.2 Analog Output With Gain Because the maximum analog output from the TAS3002 device is 0.707 V , the output level can be increased by using an external amplifier. The circuit shown in Figure 3−3 boosts the output level to 1 V (when it has a gain of 1.414) and provides improved signal-to-noise ratio (SNR).
  • Page 16 3.2.3 Reference Voltage Filter Figure 3−4 shows the TAS3002 reference voltage filter. 0.1 F 15 F 0.1 F 0.1 F V REFP TAS3002 Figure 3−4. TAS3002 Reference Voltage Filter 3−3...
  • Page 17 3−4...
  • Page 18 C bus. Subsequent assertions of the mute GPI terminal toggle soft mute off and on. 4.3 Input Mixer Control The TAS3002 device is capable of mixing and multiplexing three channels (SDIN1, SDIN2, and the ADC output) of serial audio data. The mixing is controlled through three mixer control registers. This is accomplished by loading values into the corresponding bytes of the mixer left gain (07h) and mixer right gain (08h) control registers.

  • Page 19: Treble Control

    4.4 Mono Mixer Control The TAS3002 device contains a second mixer that performs the function of mixing left and right channel digital audio data from the input mixer in order to derive a monaural channel. This mixer has a fixed gain of −6 dB so that full scale inputs on L_sum and R_sum do not produce clipping on the resulting L+R_sum.

  • Page 20: Bass Control

    4.6 Bass Control The bass gain level can be adjusted within the range of 15 dB to −15 dB with 0.5-dB step resolution. The level changes are accomplished by downloading bass codes (shown in NO TAG) into the bass frequency control register. Alternatively, a limited range of bass control is available by asserting the bass-up or bass-down GPI terminal (see Section 7.6.1).
  • Page 21 4.8 Analog Control Register (40h) The analog control register (ACR) allows control of de-emphasis, selection of the analog input channel to the ADC, and analog power down. An I C master is required to write the appropriate command into the ACR. The ACR subaddress is 40h. Type Default Table 4−1.
  • Page 22 Some have even reached the acceptance level of ISO recommendation. The TAS3002 device has a simplified loudness contour algorithm that diminishes the effect of weak bass at low listening levels. Since contour has volume level dependency, the user must define the relation between the gain of the contour circuit and the volume level.
  • Page 23 4.10 Dynamic Range Compression/Expansion (DRCE) The TAS3002 device provides the user with the ability to manage the dynamic range of the audio system. The DRCE receives data, and affects scaling after the volume/loudness block. As shown in Figure 4−4, the DRCE is applied after the volume/loudness control block as a DRCE scale factor.
  • Page 24 4.12 Main Control Register 1 (01h) The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2 (MCR2). The MCR1 register contains the bits associated with load speed, SCLK frequency, serial-port mode, and serial-port word length.
  • Page 25 4−8...
  • Page 26 5.1.1 Filter Coefficients The filter coefficients for the TAS3002 device are downloaded through the I C port and loaded into the biquad memory space. Each biquad filter memory space has an independent address. Digital audio data coming into the device is processed by the biquad block and then converted into analog waveforms by the DAC.
  • Page 27 5−2...
  • Page 28 An external pullup resistor must be used to set the high level on the bus. The TAS3002 device operates in standard mode up to 100 kbps with as many devices on the bus as desired up to the capacitance load limit of 400 pF.

  • Page 29: Operation

    6.3 Operation The 7-bit address for the TAS3002 device is 0110 10X R/W where X is a programmable address bit, set by terminal 7 (CS1). Combining CS1 and the R/W bit, the TAS3002 device can respond to four different I C addresses (two read and two write).
  • Page 30 C Stop command. NOTES: 1. The TAS3002 will appear to be locked up, if a Send Ack is issued after the last byte read. It is required to send an I 2 C Stop command after the last byte and not a Send Ack.

  • Page 31: Smbus Operation

    Block Write Protocol The TAS3002 device supports the block write protocol that allows up to 32 bytes to be sent as a block. To send a command using this format, the most significant bit (MSB) of the TAS3002 subaddress must be set high and the subaddress (also with MSB set high) must be programmed into the SMBus command byte.

  • Page 32: Wait States

    200 ms between transactions. 6.4.4 TAS3002 SMBus Readback The TAS3002 device supports a subset of SMBus readback. When an SMBus read command is sent to the device (LSB = high), it answers with the subaddress and the last six bytes written. SMBus...
  • Page 33 6−6...

  • Page 34: Microcontroller Operation

    Section 7.2.2 for default values. If the TAS3002 address is 68h (ADDR_SEL=0), it becomes the bus master device and attempts to load parameters and coefficients from the external EEPROM. If no EEPROM is present, the TAS3002 device remains in its default condition.

  • Page 35: Reset Circuit

    In the case where the system power supplies are slow in reaching their final voltage or where there is a difference in the time the system power supplies take to become stable, the TAS3002 reset can be delayed by a simple RC circuit.

  • Page 36: Power Down Mode

    7.3 Power-Down Mode The TAS3002 device has an asynchronous power-down mode. In the power-down mode, the internal control registers and equalization programming of the device are stored in the device. To enter power-down mode: 1.

  • Page 37: Test Mode

    1 ms Figure 7−2. Power-Down Timing Sequence In power-down mode, the TAS3002 device typically consumes less than 1 mA. 7.4 Test Mode Terminal 9 (TEST) is tied low in normal operation. This function is reserved for factory test and must not be asserted.
  • Page 38 NOTE: x = Logic low Initially (after reset), the TAS3002 GPI is set to control volume, bass, and treble. Simultaneously setting GPI bits 1 and 5 low for 1 second changes the function of the GPI terminals to control mute and equalization.
  • Page 39 Start Power Up Restore Volume Initialize Default and MCR Initialize TAS3002 EEPROM TAS3001 Load Parameters Slave Write and Coefficients to DSP Volume/Bass/Treble Up/Down Echo to TAS3001 Switch BQ Set Save Volume, Mute Power Down Save PWR_DN Stop PLL Stop DRC_OFF Figure 7−3.
  • Page 40 7.7 External EEPROM Memory Maps Table 7−2 through Table 7−5 show the 512-byte and 2048-byte EEPROM memory maps. Table 7−2. 512-Byte EEPROM Memory Map 2.0 Channels ADDRESS BYTE NUMBER FUNCTION 000h Signature (2Ah) 001h ID byte = 0000 0000 002h 003h−00Bh Mixer left gain 00Ch−014h...
  • Page 41 Volume NOTE: In this mode, the TAS3002 and the TAS3001 devices both use the same equalization coefficients for their right and left channels. Bytes are in the same order as they appear in the I 2 C register map. The EEPROM address is A0h.
  • Page 42 Table 7−4. 2048-Byte EEPROM Memory Map—2.0 Speakers With Multiple Equalizations TAS3002 ADDRESS NUMBER TAS3002 ADDRESS FUNCTION CATEGORY TAS3001 LEFT BIQUAD OF BYTES RIGHT BIQUAD 000h Signature (2Ah) 001h 002h 1EFh 003h−00Bh Mixer left gain 1F0h−1F2h 00Ch−014h Mixer right gain 1F3h−1F5h 015h−019h...
  • Page 43 Table 7−5. 2048-Byte EEPROM Memory Map—2.1 Speakers With Multiple Equalizations NUMBER TAS3001 ADDRESS TAS3001 ADDRESS TAS3002 ADDRESS FUNCTION CATEGORY OF BYTES LEFT CHANNEL RIGHT CHANNEL 000h Signature (2Ah) 001h 002h 1EFh 003h−00Bh Mixer left gain 1F0h−1F2h 00Ch−014h Mixer right gain 1F3h−1F5h...

  • Page 44: Electrical Characteristics

    8 Electrical Characteristics † 8.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range: ............−0.3 V to 3.6 V .
  • Page 45 8.4 ADC Digital Filter = 25 C, AV = 3.3 V, DV = 3.3 V, f = 48 kHz, 20-bit I S mode All terms characterized by frequency are scaled with the chosen sampling frequency, f . See Figure 8−1 through Figure 8−4 for performance curves of the ADC digital filter.

  • Page 46: Analog-To-Digital Converter

    0.008 0.006 0.004 0.002 −0.002 0.1 f s 0.2 f s 0.3 f s 0.4 f s 0.5 f s f − Frequency − Hz Figure 8−3. ADC Digital Filter Pass-Band Characteristics −0.2 −0.4 −0.6 −0.8 −1 1 f s 2 f s 3 f s 4 f s...

  • Page 47: Input Multiplexer

    8.6 Input Multiplexer = 25 C, AV = 3.3 V, DV = 3.3 V, f = 48 kHz, 20-bit I S mode PARAMETER TEST CONDITIONS UNIT Input impedance Crosstalk Full-scale input voltage range V PP 8.7 DAC Interpolation Filter = 25 C, AV = 3.3 V, DV = 3.3 V, f = 48 kHz, 20-bit I...

  • Page 48: Digital-To-Analog Converter

    8.8 Digital-to-Analog Converter = 25 C, AV = 3.3 V, DV = 3.3 V, f = 48 kHz, input = 0 dB-f sine wave at 1 kHz PARAMETER TEST CONDITIONS UNIT SNR (EIAJ) A weighted Dynamic range −60 dB, 1 kHz Signal to (noise + distortion) ratio 0 dB, 1 kHz, 20 Hz to 20 kHz Power supply rejection ratio...
  • Page 49 8.10 I C Serial Port Timing Characteristics UNIT f (SCL) SCL clock frequency t (buf) Bus free time between start and stop t (low) Low period of SCL clock t (high) High period of SCL clock t h(sta) Hold time repeated start t su(sta) Setup time repeated start t h(dat) Data hold time (See Note 6)

  • Page 50: System Diagrams

    9 System Diagrams Figure 9−1 and Figure 9−2 show the TAS3002 stereo and 2.1-channel applications, respectively. +3.3 V DD RESET Analog Out Analog In TAS3002 SPDIF I 2 S I 2 C EEPROM Master B-T-V-EQ Switches NOTE: Items such as the PLL network and power supplies are omitted for clarity.
  • Page 51 B-T-V-EQ-Sub Vol on GPIO L+R Mix I 2 C Slave I 2 S PCM1744 Analog Out TAS3001 Address = 6Ah NOTE: Items such as the PLL network and power supplies are omitted for clarity. Figure 9−2. TAS3002 Device, 2.1 Channels 9−2...

  • Page 52: Mechanical Information

    10 Mechanical Information The TAS3002 device is packaged in a 48-terminal PFB package. The following illustration shows the mechanical dimensions for the PFB package. PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 5,50 TYP 7,20 Gage Plane...
  • Page 53 Op Temp (°C) Top-Side Markings Samples Drawing TAS3002PFB OBSOLETE TQFP Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 TAS3002 & no Sb/Br) TAS3002PFBG4 OBSOLETE TQFP Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 TAS3002 & no Sb/Br) TAS3002PFBR...
  • Page 54 PACKAGE OPTION ADDENDUM www.ti.com 3-Apr-2013 Addendum-Page 2...

  • Page 55: Tape And Reel Information

    PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) TAS3002PFBR TQFP 330.0 16.4 12.0 16.0 Pack Materials-Page 1...
  • Page 56 PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) TAS3002PFBR TQFP 367.0 367.0 38.0 Pack Materials-Page 2...

  • Page 57: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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