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M
K
7
7
M
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M
K
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7
M
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7
7
M
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M
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D
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Channel for communications between the memory and surrounding devices.
E
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E
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The ECC mode needs 8 ECC bits for 64-bit data. Each time memory is accessed; ECC bits are updated and checked by a
special algorithm. The ECC algorithm has the ability to detect double-bit error and automatically correct single-bit error while
parity mode can only detect single-bit error.
E
D
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E
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t
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n
d
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d
D
a
E
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The EDO DRAM technology is actually very similar to FPM (Fast Page Mode). Unlike traditional FPM that tri-states the memory
output data to start the pre-charge activity, EDO DRAM holds the memory data valid until the next memory access cycle, that is
similar to pipeline effect and reduces one clock state.
E
E
P
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E
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c
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E
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2
Also known as E
PROM. Both EEPROM and
technology is different. Size of EEPROM is much smaller than flash ROM.
M
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Flash ROM
)
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y
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a
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a
m
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can be re-programmed by electronic signals, but the interface
78
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