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A
X
4
5
S
-
5
3
3
/
A
X
A
X
4
5
S
-
5
3
3
/
A
X
D
M
A
(
D
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e
c
t
M
e
m
o
D
M
A
(
D
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c
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m
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Channel for communications between the memory and surrounding devices.
E
C
C
(
E
r
r
o
r
C
h
e
c
k
i
n
E
C
C
(
E
r
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n
The ECC mode needs 8 ECC bits for 64-bit data. Each time memory is accessed; ECC bits are updated and checked by a special
algorithm. The ECC algorithm has the ability to detect double-bit error and automatically correct single-bit error while parity mode can only
detect single-bit error.
E
D
O
(
E
x
t
e
n
d
e
d
D
a
E
D
O
(
E
x
t
e
n
d
e
d
D
a
The EDO DRAM technology is actually very similar to FPM (Fast Page Mode). Unlike traditional FPM that tri-states the memory output data
to start the pre-charge activity, EDO DRAM holds the memory data valid until the next memory access cycle, that is similar to pipeline effect
and reduces one clock state.
E
E
P
R
O
M
(
E
l
e
c
t
r
o
n
E
E
P
R
O
M
(
E
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c
t
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o
n
2
Also known as E
PROM. Both EEPROM and
different. Size of EEPROM is much smaller than flash ROM.
E
P
R
O
M
(
E
r
a
s
a
b
l
e
P
E
P
R
O
M
(
E
r
a
s
a
b
l
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P
Traditional motherboard stores BIOS code in EPROM. EPROM can only be erased by ultra-violet (UV) light. If BIOS has to be upgraded,
you need to remove EPROM from motherboard, clear by UV light, re-program, and then insert back.
4
5
S
-
5
3
3
N
4
5
S
-
5
3
3
N
r
y
A
c
c
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s
s
)
r
y
A
c
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)
g
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d
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g
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)
t
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m
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i
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P
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g
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E
r
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a
b
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e
P
r
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g
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a
Flash ROM
r
o
g
r
a
m
m
a
b
l
e
R
O
M
r
o
g
r
a
m
m
a
b
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R
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m
m
a
b
l
e
R
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)
m
m
a
b
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)
can be re-programmed by electronic signals, but the interface technology is
)
)
85
O
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e
M
a
n
u
a
l
O
n
l
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e
M
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a
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