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M
K
7
3
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E
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K
7
3
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P
B
S
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A
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For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits).
PBSRAM only needs one address decoding time and automatically sends the remaining QWords
to CPU according to a predefined sequence. Normally, it is 3-1-1-1, total 6 clocks, which is faster
than asynchronous SRAM. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU. Slot 1
and Socket 370 CPU do not need PBSRAM.
P
P
C
C
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-
1
1
0
0
0
0
D
D
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M
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M
M
SDRAM
DIMM that supports 100MHz CPU
P
P
C
C
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-
1
1
3
3
3
3
D
D
I
I
M
M
M
M
SDRAM
DIMM that supports 133MHz CPU
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C
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C
Bus for the internal connection of peripheral devices, high-speed data channel between the
computer and expansion card.
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t
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A
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)
FSB
bus clock.
FSB
bus clock.
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