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A
X
4
T
-
5
3
3
P
r
o
A
X
4
T
-
5
3
3
P
r
o
P
P
a
a
r
r
i
i
t
t
y
y
B
B
i
i
t
t
The parity mode uses 1 parity bit for each byte, normally it is even parity mode, that is, each time the memory data is updated,
parity bit will be adjusted to have even count "1" for each byte. When next time, if memory is read with odd number of "1", the
parity error is occurred and this is called single bit error detection.
P
B
S
R
A
M
(
P
i
p
e
l
i
n
e
P
B
S
R
A
M
(
P
i
p
e
l
i
n
e
For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits). PBSRAM only needs one address
decoding time and automatically sends the remaining QWords to CPU according to a predefined sequence. Normally, it is
3-1-1-1, total 6 clocks, which is faster than asynchronous SRAM. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU.
Slot 1 and Socket 370 CPU do not need PBSRAM.
P
C
-
1
0
0
D
I
M
M
P
C
-
1
0
0
D
I
M
M
SDRAM
DIMM that supports 100MHz CPU
P
C
-
1
3
3
D
I
M
M
P
C
-
1
3
3
D
I
M
M
SDRAM
DIMM that supports 133MHz CPU
d
B
u
r
s
t
S
R
A
M
)
d
B
u
r
s
t
S
R
A
M
)
FSB
bus clock.
FSB
bus clock.
O
O
98
n
l
i
n
e
M
a
n
u
a
l
n
l
i
n
e
M
a
n
u
a
l
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