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142 Agilent E1330B Digital I/O Module Register Information
/* port 3 */
ibpoke((base_addr + port_hand_1),0x00);
ibpoke((base_addr + port_del_1),0x00);
ibpoke((base_addr + port_norm_1),0x00);
ibpoke((base_addr + port_ctl_1),0x00);
ibpoke((base_addr + port_xfr_1),0x00);
ibpoke((base_addr + port_data_1),pattern_2);
/* return ports back to input state */
ibpoke((base_addr + port_ctl_0),0x40);
ibpoke((base_addr + port_xfr_0),0x00);
ibpoke((base_addr + port_ctl_1),0x40);
ibpoke((base_addr + port_xfr_0),0x00);
/* input a data byte at port 2, no handshake */
ibpoke((base_addr + port_hand_2),0x00);
ibpoke((base_addr + port_del_2),0x00);
ibpoke((base_addr + port_norm_2),0x00);
ibpoke((base_addr + port_ctl_2),0x40);
ibpoke((base_addr + port_xfr_2),0x00);
data_byte = ibpeek(base_addr + port_data_2);
printf(("port data register value = %02X\n",data_byte);
/* input a data byte at port 1, leading edge handshake */
ibpoke((base_addr + port_hand_1),0x20);
ibpoke((base_addr + port_del_1),0xF2);
ibpoke((base_addr + port_norm_1),0x00);
ibpoke((base_addr + port_ctl_1),0x40);
ibpoke((base_addr + port_xfr_1),0x02);
count = 0;
while (test_drr(base_addr + port_xfr_1)){
count = count++;
if (count == 100) {
printf("DRR bit not ready ");
exit (-1); }
}
data_byte = ibpeek(base_addr + port_data_1);
printf(("port data register value = %02X\n",data_byte);
/* disable port handshake */
ibpoke((base_addr + port_xfr_2),0x00);
ibpoke((base_addr + port_xfr_1),0x00);
return 0; }
Appendix B
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