Instrument Status Reporting Ieee 488.2 Basics; Ieee 488.2 Model; Instrument Model Structure; Status Byte Register - Fluke 6100A User Manual

6100A
Users Manual

5-31. Instrument Status Reporting IEEE 488.2 Basics

5-32. IEEE 488.2 Model

This develops the IEEE 488.1 model into an extended structure with more definite rules.
These rules invoke the use of standard 'Common' messages and provide for device-
dependent messages. A feature of the structure is the use of 'Event' registers, each with
its own enabling register as shown in 'Retrieval of Device Status Information'.

5-33. Instrument Model Structure

The IEEE 488.2 Standard provides for an extensive hierarchical structure with the Status
Byte at the apex, defining its bits 4, 5 and 6 and their use as summaries of a Standard–
defined event structure, which must be included if the device is to claim conformance
with the Standard. The instrument employs these bits as defined in the Standard.
Bits 0, 1, 2 and 3 and 7 are available to the device designer; only bits 3 and 7 are used in
the instrument, and these are as defined by the SCPI standard. The application
programmer must recognize that whenever the application program reads the Status Byte,
it can only receive summaries of types of events, and further query messages will be
needed to probe the details relating to the events themselves. For example: a further byte
is used to expand on the summary at bit 5 of the Status Byte.

5-34. Status Byte Register

In this structure the Status Byte is held in the 'Status Byte Register'; the bits being
allocated as follows:
5-12
Subsequent Action
Thus the application programmer can enable any assigned event to cause an
SRQ, or not. The controller can be programmed to read the Status Byte, using a
serial poll to read the Status Byte register and the true summary bit (ESB or
MAV). The application program then investigates the appropriate event structure
until the causal event is discovered. The detail for each register is expanded in the
following paragraphs, and in the command descriptions.
Bits: 0 (DIO1), 1 (DIO2) and 2 (DIO3) are not used in the instrument status byte.
They are always false.
Bit 3 summarizes the state of the 'Questionable Status data', held in the
'Questionable Status register' (QSR), whose bits represent SCPI-defined and
device-dependent conditions in the instrument. The QSS bit is true when the data
in the QSR contains one or more enabled bits, which are true, or false, when all
the enabled bits in the byte are false. The SCPI Standard defines the QSR and its
data, (not used in 6100A).
Bit 4 (DIO5) IEEE 488.2 defined Message Available Bit (MAV).
The MAV bit helps to synchronize information exchange with the controller. It is
true when a message is placed in the Output Queue; or false when the Output
Queue is empty. The common command CLS can clear the Output Queue and
the MAV bit 4 of the Status Byte Register; providing it is sent immediately
following a 'Program Message Terminator'.
Bit 5 (DIO6) IEEE 488.2 defined Standard Event Summary Bit (ESB).
Summarizes the state of the 'Event Status byte', held in the 'Event Status
register' (ESR), whose bits represent IEEE 488.2 defined conditions in the