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7.3
Front-End
The Front-End consist of the following key components:
•
Tuner HD1816AF
•
SAW filter 36M125
•
IF demodulator DRX3926K
•
AGC amplifier UPC3221GV.
Below find a block diagram of the front-end application.
SAW
NXP Hybrid
Filter
Tuner
I2C-TUNER
Figure 7-4 Front-End block diagram
The DRX3926K is a multi-standard demodulator supporting
DVB-C, DVB-T and analogue standards. The demodulated
digital stream is fed into the parallel transport stream data ports
of the PNX8543. The demodulated analogue signal in the form
of CVBS is connected to the analogue video CVBS/Y input
channel, while the SIF is connected via the SSIF2 positive input
port.
7.4
HDMI
In this platform, the TDA9996 HDMI multiplexer is
implemented. Only for one HDMI input, a separate EEPROM is
implemented to store the EDID values. For the other HDMI
inputs, the EDID contents are no longer stored in a separate
EEPROM, but directly in the multiplexer. Each input has its own
physical subaddress: the first 253 bytes are common, where
the last 3 bytes define the specific input. The EDID contents
are, at +5V power-up, downloaded to RAM. The following
figures show the HDMI input configuration and EDID control.
PNX8543
A
B
H D M IA-R X
E d id
H D M I 4
(optional)
1M 96
Figure 7-5 HDMI input configuration
I2C-SSB
CVBS
IF Amplifier
DRX3926K
PNX8543
2nd SIF
TS
IF-AGC
18440_211_090227.eps
H D M IB-R X
D R X
D
Out
H D M I Side
TDA9996
(optional)
C R X
AR X
B
BR X
H D M I 3
H D M I 2
H D M I 1
(optional)
18440_213_090227.eps
Circuit Descriptions
P la tfo rm w ith e m b e d d e d E D ID
Figure 7-6 EDID control (embedded EDID)
090227
The delta's with respect to the use of the TDA9996 as HDMI
multiplexer compared with earlier chassis/platforms are:
•
+5V detection mechanism
•
Stable clock detection mechanism
•
Integrated EDID
•
RT control
•
HPD control
•
TMDS output control
•
CEC control
•
New hotplug control for PNX8543 for 5th HDMI input
•
New EDID structure: EDID stored in TDA9996, therefore
there are no EDID pins on the SSB. Only in the event of a
5th HDMI input, an additional EEPROM is foreseen, as
was implemented in previous platforms.
After replacement of the TDA9996 HDMI mux, the default I
address should be reprogrammed from C0 to CE, and the
HDMI EDIDs should be reprogrammed as well. Both actions
should be executed via ComPair.
7.5
Video and Audio Processing - PNX8543
The PNX8543 is the main audio and video processor (or
System-on-Chip) for this platform. It is a member of the
PNX85xx SoC family (described in earlier chassis) with the
addition of the MPEG4 functionality; the separate STi710x
MPEG4 decoder is no longer implemented in this platform.
Some more delta's compared to the previous PNX85xx are:
•
2 HDMI inputs (A & B)
•
HDMI deep colour RGB/YCbCr 4:4:1 10/12 bit detection.
The PNX8543 handles the digital and analogue audio- and
video decoding and processing. The processor is a MIPS32
general purpose CPU and a 8051-based TV controller for
power management and user event handling.
•
For a functional diagram of the PNX8543, refer
to
Figure
090227
Q549.2E LA
E D ID : 2 5 3B
IIC
TDA 9996
3B
3B
3B
3B
2 5 3 co m m o n B yte s
+ 1B su b a d d re s o f
S o u rce P h ys ica l A d d re ss
+3B fo r inp u t A
+3B fo r inp u t B
4 × H D M I
+3B fo r inp u t C
inputs
+3B fo r inp u t D
7-7.
7.
EN 45
CPU
18440_214_090227.eps
090227
2
C
2009-May-08
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