Nvidia NFORCE 780I SLI User Manual page 86

780i 3-Way SLI Motherboard
W to R Command Delay
q
The Write-to-Read (tWRD) command delay is the amount of cycles required
between a valid write command and the next read command. A lower cycle
time results in better performance but is can instability. Adjustable from 0 to
6 cycles.
W to W Timing
q
The Write-to-Write (tWRWR) timing is the number of clock cycles between
the last write and the subsequent Write command to the same physical bank.
Adjustable from 2 to 15 cycles.
CAS Latency
q
The CAS Latency (tCL) is the time (in number of clock cycles) that elapses
after the memory controller sends a request to read a memory location and
before the data is sent to the module's output pins. The value shown cannot
be changed.
Clock Drive Strength
q
This value is filled in by the system and can not be changed by the user.
Command Per Clock
q
The Command Per Clock (tCPC) sets the Command Rate for the memory
controller. The value shown cannot be changed
Async Latency
q
This value is filled in by the system and can not be changed by the user.
NVIDIA Corporation
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October 17, 2007 | DU-03597-001_v01