Texas Instruments Extensa 60x Series Maintenance Manual page 79

Table 5-3 Self Test Beep Messages
Beep Code Port 80h
None 01h
1-1-3 02h
1-1-4 03h
1-2-1 04h
1-2-2 05h
1-2-3 06h
1-3-1 08h
None 09h
1-3-3 0Ah
1-3-4 0Bh
1-4-1 0Ch
1-4-2 0Dh
2-1-1 10h
2-1-2 11h
2-1-3 12h
2-1-4 13h
2-2-1 14h
2-2-2 15h
2-2-3 16h
2-2-4 17h
2-3-1 18h
2-3-2 19h
2-3-3 1Ah
2-3-4 1Bh
2-4-1 1Ch
2-4-2 1Dh
2-4-3 1Eh
2-4-4 1Fh
3-1-1 20h
3-1-2 21h
3-1-3 22h
Description
CPU Register Test in Progress
CMOS Write/Read Failure
ROM BIOS Checksum Failure
Programmable Interval Timer Failure
DMA Initialization Failure
DMA Page Register Write/Read Failure
DRAM Refresh Verification Failure
1ST 64K RAM Test in Progress
1ST 64K RAM Chip or Data line Failure
1ST 64K RAM Odd/Even Logic Failure
Address Line Failure, 1ST 64K RAM
Parity Failure, 1ST 64K RAM
Bit 0, 1ST 64K RAM Failure
Bit 1, 1ST 64K RAM Failure
Bit 2, 1ST 64K RAM Failure
Bit 3, 1ST 64K RAM Failure
Bit 4, 1ST 64K RAM Failure
Bit 5, 1ST 64K RAM Failure
Bit 6, 1ST 64K RAM Failure
Bit 7, 1ST 64K RAM Failure
Bit 8, 1ST 64K RAM Failure
Bit 9, 1ST 64K RAM Failure
Bit A, 1ST 64K RAM Failure
Bit B, 1ST 64K RAM Failure
Bit C, 1ST 64K RAM Failure
Bit D, 1ST 64K RAM Failure
Bit E, 1ST 64K RAM Failure
Bit F, 1ST 64K RAM Failure
Slave DMA Register Failure
Master DMA Register Failure
Master Interrupt Mask Register Failure
Troubleshooting Procedures 5-9