Embeddedice-Rt Register Map; Monitor Mode Debugging; Table 9-1 Function And Mapping Of Embeddedice-Rt Registers - Epson ARM720T Core Cpu Manual

9: Debugging Your System
9.8

EmbeddedICE-RT register map

The locations of the EmbeddedICE-RT registers are shown in Table 9-1.

Table 9-1 Function and mapping of EmbeddedICE-RT registers

Address
b00000
b00001
b00100
b00101
b01000
b01001
b01010
b01011
b01100
b01101
b10000
b10001
b10010
b10011
b10100
b10101
9.9

Monitor mode debugging

The ARM720T processor contains logic that enables the debugging of a system without
stopping the core entirely. This means that critical interrupt routines continue to be serviced
while the core is being interrogated by the debugger.
9.9.1 Enabling monitor mode
The debugging mode is controlled by bit 4 of the Debug Control Register (described in
control register
on page 9-39). Bit 4 of this register is also known as the monitor mode enable
bit:
Bit 4 set
Bit 4 clear
9-12
Width Function
6 Debug control
5 Debug status
32 Debug Communications Channel (DCC) control register
32 Debug Communications Channel (DCC) data register
32 Watchpoint 0 address value
32 Watchpoint 0 address mask
32 Watchpoint 0 data value
32 Watchpoint 0 data mask
9 Watchpoint 0 control value
8 Watchpoint 0 control mask
32 Watchpoint 1address value
32 Watchpoint 1 address mask
32 Watchpoint 1 data value
32 Watchpoint 1 data mask
9 Watchpoint 1 control value
8 Watchpoint 1 control mask
Enables the monitor mode features of the ARM720T processor.
When this bit is set, the EmbeddedICE-RT logic is configured so
that a breakpoint or watchpoint causes the ARM720T core to enter
abort mode, taking the Prefetch or Data Abort vectors respectively.
Monitor mode debugging is disabled and the system is placed into
halt mode. In halt mode, the core enters debug state when it
encounters a breakpoint or watchpoint.
EPSON ARM720T CORE CPU MANUAL
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