Noise Level In Ds / Qs Mode; Steadyclock - RME Audio Hammerfall HDSP 9632 User Manual

33.6 Noise level in DS / QS Mode

The outstanding signal to noise ratio of the HDSP 9632's AD-converters can be verified even
without expensive test equipment, by using record level meters of various software. But when
activating the DS and QS mode, the displayed noise level will rise from -109 dB to -104 dB at 96
kHz, and –82 dB at 192 kHz. This is not a failure. The software measures the noise of the whole
frequency range, at 96 kHz from 0 Hz to 48 kHz (RMS unweighted), at 192 kHz from 0 Hz to 96
kHz.
When limiting the measurement's frequency range to 22 kHz (audio bandpass, weighted) the
value would be -109 dB again. This can be verified even with RME's Windows tool DIGICheck.
Although a dBA weighted value does not include such a strong bandwidth limitation as audio
bandpass does, the displayed value of –108 dB is nearly identical to the one at 48 kHz.
The reason for this behaviour is the noise shaping technology of the analog to digital convert-
ers. They move all noise and distortion to the in-audible higher frequency range, above 24 kHz.
That's how they achieve their outstanding performance and sonic clarity. Therefore the noise is
slightly increased in the ultrasound area. High-frequent noise has a high energy. Add the dou-
bled (quadrupled) bandwidth, and a wideband measurement will show a siginificant drop in
SNR, while the human ear will notice absolutely no change in the audible noise floor.

33.7 SteadyClock

The SteadyClock technology of the HDSP 9632 guarantees an excellent performance in all
clock modes. Thanks to a highly efficient jitter suppression, the AD- and DA-conversion always
operates on highest sonic level, being completely independent from the quality of the incoming
clock signal.
SteadyClock has been originally de-
veloped to gain a stable and clean
clock from the heavily jittery MADI data
signal (the embedded MADI clock
suffers from about 80 ns jitter). Using
the 9632's input signals SPDIF, ADAT
or word clock, you'll most probably
never experience such high jitter val-
ues. But SteadyClock is not only ready
for them, it would handle them just on
the fly.
Common interface jitter values in real
world applications are below 10 ns, a
very good value is less than 2 ns.
The screenshot shows an extremely jittery SPDIF signal of about 50 ns jitter (top graph, yellow).
SteadyClock turns this signal into a clock with less than 2 ns jitter (lower graph, blue). The sig-
nal processed by SteadyClock is of course not only used internally, but also used to clock the
digital outputs. Therefore the refreshed and jitter-cleaned signal can be used as reference clock
without hesitation.
User's Guide HDSP System HDSP 9632 © RME
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