Acer Extensa 61X Service Manual page 78

Table 2-3 M1523 Signal Descriptions (continued)
Signal
ISA Interface
SMEMRJ / LMEGJ
SMEMWJ / RTCAS
DREQJ[7:5]
DREQJ[3:0]
DACKJ[7:5] /
DAK_SEL[2:0]
DACKJ[3] / PCSJ,
DACKJ[2] /
DACKOJDACKJ[1],
DACKJ[0]
TC
REFSHJ
Timer
SPKR
Miscellaneous
SPLED
ROMCSJ
XDIR
KBINH/ IRQ1
KBCLK/ KBCSJ
KBDATA
Major Chips Description
Pin Type
176 O
174 O
38, 34, 30, I
186, 166, 189,
25
36,32, O
28,
184,
204,
48, I/O
47 O
206 O
191 I/O
43 O
44 O
158 O
159 O
151 I
152 I/O
153 O
Description
ISA System Memory Read. When the internal RTC is
enabled, this signal indicates that the memory read cycle
is for an address below 1-MB address. Otherwise, this pin
only indicates an address below 1M byte.
ISA System Memory Write. When the internal RTC is
enabled, this signal indicates that the memory write cycle
is for an address below 1-MB address. Otherwise, this pin
is used as RTC address strobe.
DMA Request Signals.
signals.
When DACKJ polling mode is disabled, these pins are
DACKJ[7:5,3:0](O).
DAK_SEL[2:0](O) connect to external MUX select inputs,
PCSJ(O) programmable chip select, and DACKOJ(O)
connected to external MUX chip enable.
DMA End of Process. Hardware setting options:
Pulled low: Support external I/O APIC mode
Pulled high: Not support external I/O APIC
ISA Refresh Cycle. This signal is input during ISA master
cycles, but an output during other cycles.
Speaker Output. Hardware setting options:
Pulled low: Enable Internal KBC
Pulled high: Disable Internal KBC
Speed LED Output. Hardware setting options:
Pulled low: Enable DMA DACKJ[7:5,3:0]
polling mode
Pulled high: Disable DMA DACKJ[7:5;3:0]
polling mode
ROM and RTC Chip Select. This signal must be pulled
high for normal operation.
X-bus Direction Control. Hardware setting option: must be
pulled high.
KB Inhibit Input when the internal KBC is enabled.
IRQ1 Input when the internal KBC is disabled
KB interface CLK when the internal KBC is enabled.
KB Chip Select when the internal KBC is disabled
KB interface Data when the internal KBC is enabled.
These are DMA request input
Otherwise, these pins are
2-21