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A.1.2
Solving the 137 Gigabyte Capacity Barrier
As described earlier, the issue causing the 137-gigabyte barrier is the 28-
bit addressing method of the original ATA specification. A change to
expand this method was required to provide more address bits for the
interface, allowing significant growth for many years to come. A critical
issue in expanding the addressing capability was maintaining
compatibility with the existing installed base of products.
The new ATA standard, ATA/ATAPI-6, resolves this issue by increasing
the maximum number of bits used for addressing from 28 to 48. This
solution increases the maximum capacity of an ATA device to 144
petabytes while maintaining compatibility with current ATA products.
A.1.3
How is the Extension Implemented?
The 48-bit Address feature set provides a method to address devices with
capacities up to approximately 144 petabytes by increasing the number
of bits used to specify logical block addresses (LBAs) from 28 to 48. The
feature set also provides a method to increase the number of sectors that
can be transferred by a single command from 256 to 65,536 by
increasing the number of bits specifying sector count to 16 bits.
New commands specific to this feature set have been defined so that
devices can implement the new feature set in addition to previously
defined commands. Devices implementing the 48-bit Address feature set
commands will also implement commands that use 28-bit addressing in
order to maintain interoperability with older system components. In
addition, 8-bit and 48-bit commands may be intermixed.
The 48-bit Address feature set operates in LBA addressing only. Support
of the 48-bit Address feature set is indicated in the IDENTIFY DEVICE
response data. In a device implementing the 48-bit Address feature set,
the registers used for addressing are, in fact, a two-byte deep FIFO. Each
time one of these registers is written, the new content written is placed
into the "most recently written" location and the previous content of the
register is moved to "previous content" location. A host may read the
"previous content" of the registers by first setting a bit in the Device
Control register to 1 and then reading the desired register.
A.1.4
What Do the Drives Need to Meet the Spec?
The challenge to drive manufacturers is to develop and implement new
interface chips on drives that can accept and decode the new 48-bit
addressing scheme. Many functions of decoding the commands sent to
and from the drive are automated in the silicon of the drive interface
ASIC, and this is where drive manufacturers must update their designs.
Maxtor is the leader in development efforts and is the first to deliver a
product with the capacity and drive technology to deliver greater than
137 gigabytes of capacity.
Quickview 300 80/100/120/160/200/250/300GB PATA
Breaking the 137GB Storage Barrier
A-3
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