Dma Timing; Multi-Word Dma Data Transfer - Maxtor 51536H2 Installation Manual

AT INTERFACE DESCRIPTION

DMA Timing

DMA Timing
DMA Timing DMA Timing DMA Timing
T IMIN G PARAMET ERS
t0 Cycle Ti me (min)
tC DMAC K to DMARQ delay
tD DIOR-/D IOW- (min)
tE DIOR- data access (min)
tF DIOR- data hold (min)
tG DIOR-/DIOW- data setup (min)
tH DIOW- data hold (min)
tI DM AC K to DIOR-/D IOW - setup (min)
tJ DIOR-/DIOW- to DMAC K hold (min)
tKr DIOR- negated puls e wi dth (min)
tKw D IOW - negated puls e width (min)
tLr DIOR- to D MARQ delay (max)
tLw DIOW- to D MARQ delay (max)
tZ DMAC K- to tristate (max)
5 – 4
MODE 0 MODE 1 MODE 2
480 ns 150 ns 120 ns
215 ns 80 ns 70 ns
150 ns 60 ns
5 ns 5 ns 5 ns
100 ns 30 ns 20 ns
20 ns 15 ns 10 ns
0 0 0
20 ns 5 ns 5 ns
50 ns 50 ns 25 ns
215 ns 50 ns 25 ns
120 ns 40 ns 35 ns
40 ns 40 ns 35 ns
20 ns 25 ns 25 ns
Figure 5 - 3

Multi-word DMA Data Transfer