Pin Description Table - Maxtor 51536H2 Installation Manual

AT INTERFACE DESCRIPTION

Pin Description Table

Pin Description Table
Pin Description Table Pin Description Table Pin Description Table
PIN NAME PIN I/O
RESET - 01 I
D D0 17 I/O
D D1 15 I/O
D D2 13 I/O
D D3 11 I/O
D D4 09 I/O
D D5 07 I/O
D D6 05 I/O
D D7 03 I/O
D D8 04 I/O
D D9 06 I/O
DD 10 08 I/O
D D11 10 I/O
DD 12 12 I/O
DD 13 14 I/O
DD 14 16 I/O
DD 15 18 I/O
D MARQ 21 O
DIOW - 23 I
STOP
D IOR - 25 I
HD MARDY
-
HSTROBE
IORDY 27 O
DD MARDY
-
DSTROBE
CSEL 28
D MACK - 29 I
INTRQ 31 O
IOC S16 32
PD IAG - 34 I/O
DA0 35 I
DA1 33 I
DA2 36 I
C S0 - 37 I
C S1 - 38 I
DASP - 39 I/O
GND 02 N/A
19
22
24
26
30
40
KEY 20 N/A
5 – 2
SIGNAL NAME SIGNAL DESC RIPTION
Hos t Reset Reset si gnal from the host s ystem. Acti ve during power up and inacti ve after.
Host Data Bus 16 bit bi-directional data bus between host and dri ve. Lower 8 bi ts used for
register and EC C byte transfers. All 16 bi ts us ed for data transfers.
DM A Request This signal is used wi th DM AC K for D MA transfers . By asser ti ng thi s s ignal, the
dri ve indi cates that data is ready to be transfered to and from the host.
Host I/O Write Risi ng edge of Wr ite strobe clock s data from the hos t data bus to a regi ster on
the drive.
Host I/O Read Read strobe enabl es data from a register on the dri ve onto the host data bus.
DMA ready duri ng UltraDMA data in bursts.
Data strobe during UltraDMA data out bursts.
I/O C hannel Ready This signal may be driven low by the dri ve to insert wait states into host I/O
cycles.
D MA ready duri ng UltraDMA data out bursts.
D ata str obe during Ul traDMA data in bursts.
C able Select Us ed for Mas ter/Slave selection via cabl e. Requires s peci al cabling on host
s ystem and i nstallation of C abl e Sel ect jumper.
D MA Acknowledge This signal is used wi th DM ARQ for D MA transfers . By asser ti ng thi s s ignal, the
host is ac knowledging the recei pt of data or i s indicating that data is available.
Hos t Interrupt Interrupt to the host asserted when the dri ve requi res attenti on from the host.
Request
D evi ce 16 bit I/O Obsolete
Pas sed D i agnostic Output by dri ve when in Slave mode; Input to drive when in Master mode.
Hos t Address Bus 3 bi t binary address from the host to selec t a regis ter in the dri ve.
Host Chip Select 0 C hi p sel ec t from the host used to access the C omm and Bl ock registers in the
dri ve. Thi s si gnal i s a decode of I/O addres ses 1F0 - 1F 7 hex.
Host Chip Select 1 Chip select from the host used to access the Control registers in the drive. This
si gnal is a decode of I/O addres ses 3F6 - 3F 7 hex.
Drive Active/D ri ve Ti me-multiplexed, open collector output whi ch i ndi cates that a drive i s active, or
1 Present that
device 1 is pres ent.
Ground Si gnal ground.
Key Pin used for keyi ng the interface connector.