Pci Express Technology - HP ProLiant DL985 Introduction Manual

Figure 1. Typical parallel bus architecture
DRAM
Memory
Controller
DRAM
I/O
Bridge
RAID
Controller
PCI-X
100-MHz
NIC
Slots
The PCI and PCI-X specifications maintain full forward and backward compatibility from conventional
3.3-V, 33-MHz PCI to PCI-X 533. In other words, existing conventional 3.3-V, 33-MHz PCI,
conventional 66-MHz PCI, PCI-X 66, PCI-X 133, PCI-X 266, and PCI-X 533 add-in cards will operate
in any PCI (3.3 V) or PCI-X system. (PCI-X 133 and 66-MHz PCI systems support universal add-in
cards and 3.3-V PCI cards; however, they do not support 5-V-only PCI cards, which operate only at
33 MHz.)
Today's parallel bus system is highly cost effective with its small silicon footprint and low-frequency
design rules. However, economics are changing. Backward compatibility becomes increasingly
expensive as speeds increase. Higher bus speeds require physically shorter connections, which means
fewer potential slots. And as Moore's Law dictates, silicon cost drops over time much faster than
package and pin count. As a result, the industry is beginning to phase in PCI Express technology,
which will prove to be a more cost-effective solution to provide the bandwidth required for future
peripheral devices.

PCI Express technology

PCI Express 1.0 has a signaling rate of 2.5 Gb/s per direction per lane, for a combined receive and
transmit bandwidth of 500 MB/s. Multiple lanes can be combined to form higher bandwidth links.
For example, four lanes can be combined to form a 2-GB/s link, designated "x4" (pronounced "by
four"). Future PCI Express Gen2 is expected to use a signaling rate at least twice as fast and to add
features such as mandatory end-to-end cyclic redundancy check (CRC) and larger, more efficient
block sizes.
CPU
Standard
Peripherals
(KB, video,
mouse, etc.)
I/O
Bridge
PCI-X 133 Slots
iLO
3