Discrete Esata Controller; External Serial Ata Support; Real-Time Clock Subsystem - Intel DX58SO2 Specification

Intel Desktop Board DX58SO2 Technical Product Specification
1.7

Discrete eSATA Controller

The board provides a discrete Marvell* controller to support two eSATA connectors on
the back panel.
1.7.1

External Serial ATA Support

The red Serial ATA connectors on the back panel can be used for an external SATA
drive. They can also be used for port replication, which allows the aggregation of
multiple hard drives on each of the eSATA ports. Figure 10 on page 42 shows the
location of the External Serial ATA-compatible SATA ports on the back panel.
The Marvell 88SE6121 controller uses the PCI Express bus for data transfer with a
theoretical maximum transfer rate of 3 Gbits/sec per port. .
The discrete SATA interface supports the following RAID levels:
• RAID 0
• RAID 1
NOTE
The Marvell 88SE6121 controller supports single drive non-RAID configurations as well
as RAID configurations. For RAID configurations, you must install the RAID drivers by
pressing F6 during operating system installation. See your operating system
installation documentation for more information about installing drivers during the
installation process.
For information about
The location of the discrete SATA RAID connectors
1.8

Real-Time Clock Subsystem

A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When
the computer is not plugged into a wall socket, the battery has an estimated life of
three years. When the computer is plugged in, the standby current from the power
supply extends the life of the battery. The clock is accurate to ± 13 minutes/year at
25 ºC with 3.3 VSB applied.
NOTE
If the battery and AC power fail Date and Time values will be reset and the user will be
notified during POST.
When the voltage drops below a certain level, the BIOS Setup program settings stored
in CMOS RAM (for example, the date and time) might not be accurate. Replace the
battery with an equivalent one. Figure 1 on page 11 shows the location of the battery.
20
Refer to
Figure 11, page 43