Processor Bus Error - Intel SRMK2 - Server Platform - 0 MB RAM Technical Specifications

Location Function
CNB30LE PCICR
04h-05h
CNB30LE PCISR
06h-07h
CNB30LE ERRCMD
46h
CNB30LE ERRSTS
47h

9.3.2 Processor Bus Error

The CNB30LE does not report processor bus AERR# and BERR# error signals to the system.
(AERR# indicates an address parity error and BERR# indicates an unrecoverable processor bus
error.) Therefore, the system SMM handler does not log and report these types of errors to the
OS.
Intel ® SRMK2 Internet Server Technical Product Specification
Table 58: PCI bus error control bits
Bit Description
8 SERR# enable
6 PERR# enable
15 Detected Parity Error
14 Signaled System Error
13 Received Master Abort
12 Received Target Abort Status
8 Data Parity Detected
7 Enable SERR# on Received Target Abort
6 Enable SERR# on Transmitted Data Parity Error
5 Enable SERR# on Received Data Parity Error
4 Enable SERR# on Address Parity Error
3 Enable PERR# on Received Data Parity Error
2 Enable SERR# on ECC Uncorrectable Error
1 Enable SALERT on ECC Correctable Error
0 Enable SERR# on Received Master Abort
6 PCI Transmitted Data Parity Error
5 PCI Received Data Parity Error
4 PCI Address Parity Error
2 DRAM Uncorrectable Error
1 DRAM Correctable Error
0 Shutdown Cycle Detected
Value
1 = enable, 0 = disable
1 = enable, 0 = disable
1 = error, 0 = OK
1 = error, 0 = OK
1 = error, 0 = OK
1 = error, 0 = OK
1 = error, 0 = OK
1 = enable, 0 = disable
1 = enable, 0 = disable
1 = enable, 0 = disable
1 = enable, 0 = disable
1 = enable, 0 = disable
1 = enable, 0 = disable
1 = enable, 0 = disable
1 = enable, 0 = disable
1 = error, 0 = OK
1 = error, 0 = OK
1 = error, 0 = OK
1 = error, 0 = OK
1 = error, 0 = OK
1 = error, 0 = OK
86