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Technical Specification Update
The expected error rates for DIMMs come from three sources: Intel experimental measurements, data from a
memory component vendor, and the results from a 10 year study by a major computer manufacturer. The three
respective error rates are all stated per GB of memory: 1.5 errors per year, about 1 error per month, and 4 per
month. Since the lowest error rate was gathered over a relatively short time, and the highest error rate was
gathered over a relatively long time, these two numbers are being thrown out. The middle error number, which is
perceived as being a more accurate conservative estimate, will be used for purposes of programming the threshold
registers for single bit correctable memory errors or SECs. This number must be adjusted for geographical areas of
increased occurrence of alpha particles, which will increase error rates; such as high altitude or radioactive mineral
deposits. Past studies have shown that single bit error rates at altitudes as low as 10,000 feet are 14 times higher
than at sea level due to increased cosmic ray exposure. The highest of the three quoted error rates included
various geographical locations.
Table 4-24 shows suggested settings for different DIMM sizes. The values shown are with minimal error residue at
1X the expected average error rate. Halving the time or threshold would result in loss of error count resolution. One
register is programmed for each DIMM slot.
Table 4-24. Suggested Prescale Settings
DIMM Size
128 MB
256 MB
512 MB
1 GB
2 GB
4 GB
So even in non-RAS mode the chipset counter is still used to define how many SBEs can occur on each individual
DIMM and the counter for that DIMM is also dependant on the DIMM size.
Here are the resulting threshold values based on the DIMM size...
DIMM Size
Threshold value
-----------------------------------------------
64M
4
128M
4
256M
4 x 2
512M
4 x 4
1G
4 x 8
2G
4 x 16
4G
4 x 32
If the SBE count that occurs on a DIMM is over the corresponding threshold, then the DIMM Faulty LED will be lit,
and the SBE logging and detection will be disabled, and the DIMM will be taken off-line by BIOS.
Setting the "Memory Retest" option to "Enabled" in BIOS Setup will bring all DIMM(s) back on-line regardless of
current states.
Implication
Misleading reference.
Status
Doc. This will be corrected in a future release of Intel® Server Board SE7520JR2
TPS.
7
3-pin cable in SR1450 SATA Backplane Kit is not used with the
onboard SATA controller
Problem
In page 63 – 65 of Intel® Server Chassis SR1450 User Guide, there is lack of
documentation of the usage of a 3-pin cable in the SR1450 SATA Backplane Kit.
18
SPARECTL SEC
SPARECTL SEC
Prescale Value
128
64
32
16
8
4
Thresh_SEC Count
Prescale Unit
on a per DIMM Basis
7h = week
7h = week
7h = week
7h = week
7h = week
7h = week
Documentation Changes
4
4
4
4
4
4
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