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M S-6439 Barebone
Select Display Device
Use the field to select the type of device you want to use as the display(s) of
the system.
CPU & PCI Bus Control
Press <Enter> and the following sub-menu appears:
PCI M aster 0 WS Write
W hen [Enabled], writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select [Enabled] to support compliance with PCI specifi-
cation version 2.1.
VLink mode selection
This item lets you choose the speed mode between the North Bridge & South
Bridge.
VLink 8X Support
This item enables or disables the 8X VLink Data Rate.
System BIOS Cacheable
Selecting [Enabled] allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
Init Display First
This item specifies which VGA card is your primary graphics adapter.
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