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5 Hardware Design Files
5.1 Schematics
730_LDO_3V3
R1
R2
R3
200k
10.0k
200k
P_ADCIN1
P_ADCIN2
R6
R4
R7
51.0k
200k
51.0k
GND
U1
R12
10
DBG_ACC
100k
R23
19
SINK_EN
100k
P_ADCIN1
2
ADCIN1
P_ADCIN2
3
ADCIN2
GND
P_ADCIN3
5
ADCIN3
P_ADCIN4
7
ADCIN4
730_CC1
28
CC1
730_CC1
730_CC2
29
730_CC2
CC2
C14
C15
6
CAP_MIS
330pF
330pF
15
DRAIN
730_DRAIN
30
DRAIN
40
DRAIN_PAD
GND
11
GND
12
GND
14
GND
16
GND
17
GND
730_LDO_3V3
31
GND
34
GND
35
GND
39
GND_PAD
TPS25730DREFR
D8
150060RS 75000
GND
Red
R95
10.0k
1
R96
Q4
100k
GND
SLVUCP9A – NOVEMBER 2023 – REVISED MARCH 2024
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Decoded ADCINx
R5
200k
ADCIN1:
3
ADCIN2:
7
P_ADCIN3
P_ADCIN4
ADCIN3:
3
ADCIN4:
3
R8
51.0k
730_VIN_3V3
C1
0.1uF
38
GND
VIN_3V3
32
VBUS
33
VBUS
23
VBUS_IN
24
VBUS_IN
25
VBUS_IN
20
PPHV
730_PPHV
21
PPHV
22
PPHV
730_LDO_3V3
1
LDO_3V3
730_LDO_1V5
4
LDO_1V5
C16
C17
10uF
10uF
37
PLUG_EVENT
13
PLUG_FLIP
GND
GND
18
FAULT_IN
36
Reserved
9
I2Ct_SCL
8
I2Ct_SDA
26
Reserved
27
Reserved
R56
R75
R10
R11
R105
100k
100k
2.20k
2.20k
100k
Figure 5-1. TPS25730 Power Input Schematic
Copyright © 2024 Texas Instruments Incorporated
ADCINx CONFIG
Configuration
Minimum Voltage Configura tion:
15V
Ma ximum Voltage Configura tion
20V
Ope ra ting Curre nt:
3A
Ma ximum Curre nt:
5A
Minimum P ower Re quire d:
45W
730_VBUS_IN
C6
Place capacitors close to chip
1uF
C8
C9
C10
C11
C12
C13
0.1uF
10uF
10uF
10uF
10uF
10uF
GND
GND
GND
GND
GND
GND
GND
VBAT
SH-J1
J1
R94
P EC03DAAN
100k
SH-J2
730_LDO_3V3
VSYS
SELECTOR BATTERY VS TYPE-C
Hardware Design Files
Test Points
TP4
VSYS
TP5
730_PPHV
TP8
GND
L1
730_VBUS
D1
Blue
C2
C3
C4
C5
C7
0.01uF
0.01uF
0.01uF
0.01uF
R9
1uF
10.0k
GND
GND
GND
GND
GND
GND
VBAT
D3
Blue
R13
10.0k
GND
VS YS
D4
Blue
R14
10.0k
GND
TPS25751 Evaluation Module
730_VBUS
U2
TVS2200DRVR
GND
33
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