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4 Hardware Design Files
4.1 Schematics
Default EVM Schematic
Prima ry
PULL_UPx: 1.6 - 7V
J2
PULL_UP2
PULL_UP2_P
J5
PULL_UP1
PULL_UP1_P
J6
GND
GND
VIN: 3 - 14V
Channel-Disabling Connections
J10
VIN
VIN_P
C3
1µF
50V
TP6
GND
HYS_P
J15
J16
J17
1
1
1
2
2
2
SH-J15
SH-J16
SH-J17
R9
R10
R11
R12
50k
10.0k
619k
1.17M
0.1%
J23
GND
SENSEx Inpu ts of U1 (VSENSEx = 0 - 3.5V)
R17
J24
0
EN1_P
VOUT1_P
VOUT2_P
R21
60.4k
0.1%
TP13
J28
SENSE1_P
SENSE1_P
SENSE2_P
DNP
R25
DNP
C11
34.8k
50V
J31
0.1%
100pF
GND
R27
J33
0
EN3_P
VOUT3_P
VOUT4_P
R32
26.7k
TP18
J37
0.1%
SENSE3_P
SENSE3_P
SENSE4_P
DNP
R35
DNP
C15
130k
100pF
J39
0.1%
50V
GND
SLVUCT9 – JANUARY 2024
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VLDO_P
R3
R4
R5
DN
P
DNP
DNP
0
0
0
U1
TP3
IN_P
9
IN
1
SENSE1
SENSE1_P
2
SENSE2_P
SENSE2
3
SENSE3_P
SENSE3
4
SENSE4_P
SENSE4
HYS_P
6
HYS
DLY_TMR_P
11
DLY_TMR
REG_TMR_P
10
REG_TMR
7
FAULT
FAULTb_P
J19
J20
J21
1
1
1
2
2
2
8
UP_P
UP
SH-J19
SH-J20
SH-J21
16
DOWN
R8
DNP
R13
R14
R15
0
10.0k
619k
1.17M
TPS7H3014HFT/EM
DOWNb_P
SR_FAULTb Outpu t of U1
R18
J25
0
EN2_P
R22
49.9k
0.1%
TP14
J29
J30
SENSE2_P
FAULTb_P
DNP
DNP
R26
DNP
C12
50V
40.2k
J32
0.1%
100pF
GND
GND
R28
J34
0
Default Schematic Values:
EN4_P
VOUT1_P=1.80 V with VON=90% and VOFF=10%
R33
VOUT2_P=1.50 V with VON=90% and VOFF=10%
29.4k
TP19
VOUT3_P=0.8 V with VON=90% and VOFF=10%
J38
0.1%
SENSE4_P
VOUT4_P=0.88 V with VON=90% and VOFF=10%
DNP
R36
DNP
C16
90.9k
50V
Note: 0-Ohm resistors connecting ENx to VOUTx are
J40
0.1%
100pF
for simplicity of testing when external voltages are not
available to sense. DNP if connecting external voltage
GND
to VOUTx.
Copyright © 2024 Texas Instruments Incorporated
Optional External Reset
SENSE1_P
TP47
RESET
1
R70
DN
P
1
0.0k
C34
1µF
50V
GND
C33
1µF
50V
GND
18
TP5
PULL_UP1
PULL_UP1_P
22
EN1
EN1_P
21
EN2
EN2_P
20
EN3
EN3_P
19
EN4
EN4_P
17
TP7
PULL_UP2
PULL_UP2_P
12
SEQ_DONE
SEQ_DONE_P
13
PWRGD
PWRGD_P
VLDO_P
TP9
15
VLDO
VLDO_P
REFCAP_P
TP10
5
REFCAP
REFCAP_P
14
GND
23
Thermal_pad
C6
C7
470nF
1µF
25V
50V
GND
PWRGD & SEQ_DONE
Wait at least 2.8ms after VIN>UVLO_rise before
VLDO_P
sequencing up.
t_startup_delay = 2.8ms
R23
TP12
10.0k
TP15
PWRGD_P
FAULTb_P
PWRGD_P
C10
DNP
50V
R24
C9
DNP
DN
P
100pF
4
9.9k
50V
100pF
TP16
SEQ_DONE_P
SEQ_DONE_P
R31
DNP
C13
DN
P
49.9k
50V
100pF
Hardware Design Files
ENx Outpu ts of U1
TP1
EN1_P
EN1_P
Q1
DNP
R1
C1
DNP
DNP
DN
P
4
9.9k
50V
CSD13380F3
100pF
Idss_max: 50nA
GND
GND
TP2
EN2_P
EN2_P
DNP
R2
DNP
C2
DN
P
49.9k
50V
100pF
GND
TP4
EN3_P
EN3_P
DNP
R6
DNP
C4
P
DN
49.9k
50V
100pF
GND
TP8
EN4_P
EN4_P
DNP
R7
DNP
C5
DN
P
49.9k
50V
100pF
GND
SEQUENCE UP/DOWN Inpu ts (0 - 7V)
VUP > 0.6-V when VIN > 10.2 V (or 85% of 12-V)
VUP > 0.6-V after 3.7ms
VIN_P
TP11
R19
J26
UP_P
0
DNP
J27
GND
PWRGD_P
DNP
VDOWNb < 0.5-V when VIN < 6 V (or 50% of 12-V)
VIN_P
GND
TP17
R30
J35
J36
SEQ_DONE_P
DOWNb_P
0
DNP
DNP
GND
GND
TPS7H3014EVM-CVAL Evaluation Module (EVM)
J1
EN1_P
J3
EN1_P
J4
J7
EN2_P
J8
EN2_P
J9
J11
EN3_P
J12
EN3_P
J13
J14
EN4_P
J18
EN4_P
J22
R16
10.0k
UP_P
R20
C8
3.3µF
620
35V
R29
10.0k
DOWNb_P
DNP
R34
C14
909
50V
100pF
19
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