Intel SYSTEM 310 Hardware Integration Manual page 35

System 310
Calculating System Compatibility
All preconfigured systems prioritize the slots in the cardcage from
the bottom up; e.g., slot 1 is the bottom slot and has the lowest
priority. Although slots are not physically numbered, their order is
shown in Figure 5-5.
You can change the bus priority two ways: by changing the order of
the boards or by changing jumpers on the backplane. Since it is
easier to reach the boards than the jumpers, changing the order of
the boards is probably more convenient.
Boards, in all preconfigured versions of the System 310, are set up for
parallel priority resolution rather than serial priority resolution. The
System 310 backplane contains this resolution logic. Since all boards
in a MULTIBUS-based system must resolve priority in the same way,
be sure to remove the appropriate jumpers on new bus master boards.
The hardware reference manual for each Intel bus master product
explains how to make this simple change.
Board Placement Guidelines
As mentioned previously, the placement of bus master boards in the
cardcage determines the priority of that board. In preconfigured
systems, the 215G Winchester disk controller board (if present) has
the highest priority and the processor board the next highest.
The 215G disk controller occupies the highest priority slot (slot 7 at
the top of the cardcage) because this board needs the fastest access
time. Lowering its priority would slow the entire system down by
forcing the controller board to wait for a higher priority board to
relinquish the bus. Data acquisition can be further delayed by disk
latency.
In preconfigured systems, the processor board has the next highest
priority. (In preconfigured systems without a 215G board, the
processor has the highest priority.) It is located in the bottom slot,
slot 1. Although slot 1 has the lowest priority, the processor has the
second highest priority in preconfigured systems because there are no
other bus master boards between it and the controller in slot 7.
Regardless of the priority of the processor board, it must always
reside in slot 1. This is because the processor boards use the P2
connector (the smaller of the two gold-fingered card edges) for upper
address lines and the interrupt from the front panel switch. Slot 1 is
the only slot in the cardcage that provides a matching P2 edge
connector.
Once you have established the order of the bus masters in the cardcage,
synchronize them with the BCLK signal. All MULTIBUS-based systems
require a signal called BCLK (bus clock) to synchronize the operation of
the bus. Therefore, one and only one of your bus masters should
generate this signal. You can find more information on this topic and on
other MULTIBUS hardware configuration techniques in the Guide to
Configuring MULT BUS-Based Systems and the MULT BUS Handbook.
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