Diagrams - Sony NW-E305 Service Manual

Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted. (p: pF) 50 WV
or less are not indicated except for electrolytics and tantalums.
• All resistors are in Ω and
1
/ W or less unless otherwise speci-
4
fied.
• % : indicates tolerance.
• C : panel designation.
• : B+ Line.
• Voltages and waveforms are dc with respect to ground under
no-signal (detuned) conditions.
no mark : POWEN ON
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal production toler-
ances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal production toler-
ances.
• Circled numbers refer to waveforms.
• Signal path.
E : PLAY BACK
a : DIGITAL OUT
k
: DIGITAL IN
F
: FM
NW-E305/E307
SECTION 4

DIAGRAMS

Note on Printed Wiring Board
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
• : Pattern from the side which enables seeing.
Caution:
Pattern face side: Parts on the pattern face side seen from
(Side A) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Side B) the parts face are indicated.
• MAIN board is multi-layer printed board.
However, the patterns of intermediate-layer have not been in-
cluded in the diagram.
• Lead Layouts
Lead layout of conventional IC CSP (Chip Size Package)
• Waveforms
– MAIN Board –
1
IC400 <zcm (XTAL)
1.4 Vp-p
44.5 ns
500 mV/DIV, 20 ns/DIV
2
IC400 <zvz (TX)
surface
3.5 Vp-p
62.4 n s
1 V/DIV, 40 ns/DIV
3
IC401 8 (OSCOUT)
1.2 Vp-p
30.5 µs
500 mV/DIV, 20 µ s/DIV
15 15
NW-E305/E307