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Bit 5
Setting this bit to 1 enables extended arbitration. The
minimum arbitration cycle is 300 nanoseconds; this bit
extends that minimum cycle to 600 nanoseconds. This bit
is set to 0 during a system reset.
Reading this bit as a 1 indicates that a bus time-out has
occurred, and resets bit 6 in this register to O.
Bit
4
This bit is reserved and should be O.
Bits 3 -
0
These bits are undefined for a write operation and should
be set to O.
Reading these bits returns the arbitration level of the
arbiter controlling the channel during the most recent
grant state. This information allows the system
microprocessor to determine the arbitration level of the
device that caused a bus time-out.
3-6
Model 60 System Board
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