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129. DDR3 SDRAM POWER
D1241
D1241
NC
NC
TOSHIBA/1SS352
TOSHIBA/1SS352
2
1
S I
G
1 9
8 5
4
1SS352
1SS352
3.3VD
3.3VD
S I G 1 9 5 7 8
R1240
R1240
6.8KOHM
6.8KOHM
D1240
D1240
A
C
S I G 1 9 5 7 4
S I G 2 0 9 3 6
S I G 1 9 5 7 9
RB055L-30
RB055L-30
ROHM/RB055L-30
ROHM/RB055L-30
Add VTT Regulator and Related components.
1.5V
VTT_DDR
S I
G
2 0
9 7
0
VTT_DDR
MITSUMI
MITSUMI
VOLT REG. MM1851FTRE TO-252-5A
VOLT REG. MM1851FTRE TO-252-5A
IC124
IC124
UREG
UREG
[V-LMM185*]
[V-LMM185*]
1
4
Co
Co
CN
CN
2
5
VIN
VIN
VOUT
VOUT
S I G 1 9 5 7 2
3
6
S I G 1 9 5 7 7
GND
GND
HGND
HGND
MM1851FTRE
MM1851FTRE
S I
G
1 9
5 7
1
3.3VD
IC125
IC125
11
GND2
1
10
VDDQSNS
VIN
2
9
VLDOIN
S5
3
8
VTT
GND1
4
7
PGND
S3
5
6
VTTSNS
VTTREF
RT9026GFP
RT9026GFP
RICHTEK MSOP-10
RICHTEK MSOP-10
DDR TERM. REG. RT9026GFP
DDR TERM. REG. RT9026GFP
C1283
C1283
1UF/6.3V
1UF/6.3V
VTT_DDR
110 125
110 125
110 125
max: 1320mA
1.5V
110 125
110 125
S I
G
2 0
110 125
9 0
S I
6
G
1 9
110 125
5 7
0
110 125
110 125
110 125
C1281
C1281
C1282
C1282
110 125
0.01UF/25V
0.01UF/25V
2.2UF/10V
2.2UF/10V
mx_c0603
mx_c0603
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
S_DDRVREF
S_DDRVREF
125 127
S I
G
110 125
2 0
9 0
8
110 125
110 125
110 125
S I
G
1 9
5 6
6
1.5V
S I
G
1 9
5 7
6
RM135
RM135
75Ohm
75Ohm
1%
1%
M_A_DDR3_CASZ
M_A_DDR3_CASZ
1
8
M_A_DDR3_WEZ
M_A_DDR3_WEZ
2
7
M_A_DDR3_A12
M_A_DDR3_A12
3
6
S I G 1 7 4 8 2
4
5
RM136
RM136
75Ohm
75Ohm
1%
1%
M_A_DDR3_BA0
M_A_DDR3_BA0
1
8
M_A_DDR3_BA2
M_A_DDR3_BA2
2
7
M_A_DDR3_A3
M_A_DDR3_A3
3
6
S I G 1 7 4 9 1
M_A_DDR3_A0
M_A_DDR3_A0
4
5
S I G 1 7 4 9 4
RM137
RM137
75Ohm
75Ohm
1%
1%
M_A_DDR3_A1
M_A_DDR3_A1
1
8
S I G 1 7 4 9 3
M_A_DDR3_A4
M_A_DDR3_A4
2
7
S I G 1 7 4 9 0
M_A_DDR3_BA1
M_A_DDR3_BA1
3
6
M_A_DDR3_A10
M_A_DDR3_A10
4
5
S I G 1 7 4 8 4
RM138
RM138
75Ohm
75Ohm
1%
1%
M_A_DDR3_A5
M_A_DDR3_A5
1
8
S I G 1 7 4 8 9
M_A_DDR3_A2
M_A_DDR3_A2
2
7
S I G 1 7 4 9 2
M_A_DDR3_A7
M_A_DDR3_A7
3
6
S I G 1 7 4 8 7
M_A_DDR3_A9
M_A_DDR3_A9
4
5
S I G 1 7 4 8 5
RM139
RM139
75Ohm
75Ohm
1%
1%
M_A_DDR3_A14
M_A_DDR3_A14
1
8
M_A_DDR3_A8
M_A_DDR3_A8
2
7
S I G 1 7 4 8 6
M_A_DDR3_A11
M_A_DDR3_A11
3
6
S I G 1 7 4 8 3
M_A_DDR3_A6
M_A_DDR3_A6
4
5
S I G 1 7 4 8 8
M_A_DDR3_A13
M_A_DDR3_A13
R1272
R1272
75 OHM
75 OHM
1
2
S I G 1 7 4 8 1
M_A_DDR3_RASZ
M_A_DDR3_RASZ
R1273
R1273
75 OHM
75 OHM
1
2
M_A_DDR3_ODT
M_A_DDR3_ODT
R1274
R1274
75 OHM
75 OHM
1
2
M_A_DDR3_CKE
M_A_DDR3_CKE
R1275
R1275
75 OHM
75 OHM
1
2
M_A_DDR3_RESET
M_A_DDR3_RESET
M_A_DDR3_MCLKZ
M_A_DDR3_MCLKZ
R1277
R1277
75 OHM
75 OHM
1
2
M_A_DDR3_MCLK
M_A_DDR3_MCLK
R1278
R1278
75 OHM
75 OHM
1
2
MAIN BOARD
MAIN BOARD
MAIN BOARD
Size
Size
Size
Project Name
Project Name
Project Name
A4
A4
A4
Date:
Date:
Date:
Tuesday, January 29, 2013
Tuesday, January 29, 2013
Tuesday, January 29, 2013
VTT_DDR
C1244
C1244
10PF/50V
10PF/50V
S I
G
1 9
5 8
0
S I
G
1 9
5 7
5
Title :
Title :
Title :
+
+
+
!"#
!"#
!"#
Engineer:
Engineer:
Engineer:
CVP DM HW
CVP DM HW
CVP DM HW
Rev
Rev
Rev
1.00
1.00
1.00
Sheet
Sheet
Sheet
129
129
129
of
of
of
76
76
76
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