Table of Contents
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125. DDR3 SDRAM A
M_A_DDR3_A0
M_A_DDR3_A0
110 125
M_A_DDR3_A1
M_A_DDR3_A1
110 125
M_A_DDR3_A2
M_A_DDR3_A2
110 125
M_A_DDR3_A3
M_A_DDR3_A3
110 125
M_A_DDR3_A4
M_A_DDR3_A4
110 125
M_A_DDR3_A5
M_A_DDR3_A5
110 125
M_A_DDR3_A6
M_A_DDR3_A6
110 125
M_A_DDR3_A7
M_A_DDR3_A7
110 125
M_A_DDR3_A8
M_A_DDR3_A8
110 125
M_A_DDR3_A9
M_A_DDR3_A9
110 125
M_A_DDR3_A10
M_A_DDR3_A10
110 125
M_A_DDR3_A11
M_A_DDR3_A11
110 125
M_A_DDR3_A12
M_A_DDR3_A12
110 125
M_A_DDR3_A13
M_A_DDR3_A13
110 125
M_A_DDR3_A14
M_A_DDR3_A14
110 125
M_A_DDR3_BA2
M_A_DDR3_BA2
110 125
M_A_DDR3_BA1
M_A_DDR3_BA1
110 125
M_A_DDR3_BA0
M_A_DDR3_BA0
110 125
M_A_DDR3_MCLKZ
M_A_DDR3_MCLKZ
110 125
M_A_DDR3_MCLK
M_A_DDR3_MCLK
110 125
M_A_DDR3_CKE
M_A_DDR3_CKE
110 125
S I G 1 0 4 7 3
M_A_DDR3_RASZ
M_A_DDR3_RASZ
110 125
M_A_DDR3_CASZ
M_A_DDR3_CASZ
110 125
M_A_DDR3_WEZ
M_A_DDR3_WEZ
110 125
S_A_DDR3_DQM0
S_A_DDR3_DQM0
110
S_A_DDR3_DQM1
S_A_DDR3_DQM1
110
S_A_DDR3_DQS0
S_A_DDR3_DQS0
110
S_A_DDR3_DQSB0
S_A_DDR3_DQSB0
110
S_A_DDR3_DQS1
S_A_DDR3_DQS1
110
S_A_DDR3_DQSB1
S_A_DDR3_DQSB1
110
M_A_DDR3_ODT
M_A_DDR3_ODT
110 125
M_A_DDR3_RESET
M_A_DDR3_RESET
110 125 129
S_DDRVREF
S_DDRVREF
127 129
S
I G
1
0
4
0
3
1
1.5V
1.5V
1
2
1
2
C1322
C1322
C1328
C1328
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
1
2
1
2
S I G 1 0 3 4 0
S I G 1 0 3 3 8
C1323
C1323
C1329
C1329
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
1
2
1
2
S I G 1 9 9 8 3
C1324
C1324
C1330
C1330
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
1
2
1
2
C1325
C1325
C1331
C1331
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
1
2
1
2
C1326
C1326
C1332
C1332
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
1
2
1
2
S I G 1 0 3 4 1
C1327
C1327
C1333
C1333
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
IC110
IC110
H5TQ2G63DFR-PBC
H5TQ2G63DFR-PBC
DDR3 SDRAM
DDR3 SDRAM
[V-MDSD128M16]
[V-MDSD128M16]
N3
S I G 1 7 4 9 4
A0
A0
P7
S I G 1 7 4 9 3
A1
A1
P3
S I G 1 7 4 9 2
A2
A2
N2
S I G 1 7 4 9 1
A3
A3
P8
S I G 1 7 4 9 0
A4
A4
P2
S I G 1 7 4 8 9
A5
A5
R8
S I G 1 7 4 8 8
A6
A6
R2
S I G 1 7 4 8 7
A7
A7
T8
S I G 1 7 4 8 6
A8
A8
R3
S I G 1 7 4 8 5
A9
A9
L7
S I G 1 7 4 8 4
A10/AP
A10/AP
R7
S I G 1 7 4 8 3
A11
A11
N7
S I G 1 7 4 8 2
A12/BC#
A12/BC#
T3
S I G 1 7 4 8 1
A13
A13
T7
NC
NC
M7
NC
NC
M3
BA2
BA2
N8
BA1
BA1
M2
BA0
BA0
K7
/CK
/CK
J7
CK
CK
K9
CKE
CKE
L2
E3
/CS
/CS
DQL0
DQL0
J3
F7
/RAS
/RAS
DQL1
DQL1
K3
F2
/CAS
/CAS
DQL2
DQL2
L3
F8
/WE
/WE
DQL3
DQL3
E7
H3
DML
DML
DQL4
DQL4
D3
H8
DMU
DMU
DQL5
DQL5
F3
G2
DQSL
DQSL
DQL6
DQL6
G3
H7
/DQSL
/DQSL
DQL7
DQL7
C7
D7
DQSU
DQSU
DQU0
DQU0
B7
C3
/DQSU
/DQSU
DQU1
DQU1
K1
C8
ODT
ODT
DQU2
DQU2
C2
DQU3
DQU3
T2
A7
/RESET
/RESET
DQU4
DQU4
A2
DQU5
DQU5
B8
DQU6
DQU6
A3
DQU7
DQU7
J1
NC
NC
J9
NC
NC
L1
NC
NC
L9
NC
NC
R1320
R1320
2
L8
S I G 1 0 4 0 6
ZQ
ZQ
240OHM
240OHM
H1
VREFDQ
VREFDQ
0.5%
0.5%
M8
VREFCA
VREFCA
A1
B1
VDDQ
VDDQ
VSSQ
VSSQ
A8
B9
VDDQ
VDDQ
VSSQ
VSSQ
C1
D1
VDDQ
VDDQ
VSSQ
VSSQ
C9
D8
VDDQ
VDDQ
VSSQ
VSSQ
D2
E2
VDDQ
VDDQ
VSSQ
VSSQ
E9
E8
VDDQ
VDDQ
VSSQ
VSSQ
F1
F9
VDDQ
VDDQ
VSSQ
VSSQ
H2
G1
VDDQ
VDDQ
VSSQ
VSSQ
H9
G9
VDDQ
VDDQ
VSSQ
VSSQ
B2
A9
VDD
VDD
VSS
VSS
D9
B3
VDD
VDD
VSS
VSS
G7
E1
VDD
VDD
VSS
VSS
K2
G8
VDD
VDD
VSS
VSS
K8
J2
VDD
VDD
VSS
VSS
N1
J8
VDD
VDD
VSS
VSS
N9
M1
VDD
VDD
VSS
VSS
R1
M9
S I G 1 0 4 3 7
VDD
VDD
VSS
VSS
R9
P1
VDD
VDD
VSS
VSS
P9
VSS
VSS
T1
VSS
VSS
T9
VSS
VSS
1.5V
HYNIX/H5TQ2G63DFR-PBC
HYNIX/H5TQ2G63DFR-PBC
1
2
C1334
C1334
1000PF/50V
1000PF/50V
mx_c0603
mx_c0603
2
1
C1335
C1335
4.7UF/6.3V
4.7UF/6.3V
1
2
C1336
C1336
1000PF/50V
1000PF/50V
1
2
C1337
C1337
1UF/6.3V
1UF/6.3V
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
110 125
S_A_DDR3_DQ0
S_A_DDR3_DQ0
110
S I G 1 0 5 0 5
S_A_DDR3_DQ1
S_A_DDR3_DQ1
110
110 125
S_A_DDR3_DQ2
S_A_DDR3_DQ2
110
110 125
S_A_DDR3_DQ3
S_A_DDR3_DQ3
110
110 125
S_A_DDR3_DQ4
S_A_DDR3_DQ4
110
S_A_DDR3_DQ5
S_A_DDR3_DQ5
110
S_A_DDR3_DQ6
S_A_DDR3_DQ6
110
S_A_DDR3_DQ7
S_A_DDR3_DQ7
110
S_A_DDR3_DQ8
S_A_DDR3_DQ8
110
S_A_DDR3_DQ9
S_A_DDR3_DQ9
110
S_A_DDR3_DQ10
S_A_DDR3_DQ10
110
110 125
S_A_DDR3_DQ11
S_A_DDR3_DQ11
110
S_A_DDR3_DQ12
S_A_DDR3_DQ12
110
110 125 129
S_A_DDR3_DQ13
S_A_DDR3_DQ13
110
S_A_DDR3_DQ14
S_A_DDR3_DQ14
110
S_A_DDR3_DQ15
S_A_DDR3_DQ15
110
S_DDRVREF
S_DDRVREF
127 129
1.5V
1.5V
1
2
1
2
S I G 1 0 3 4 3
C1340
C1340
C1346
C1346
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
1
2
1
2
C1341
C1341
C1347
C1347
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
1
2
1
2
C1342
C1342
C1348
C1348
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
S I G 1 0 4 0 7
1
2
1
2
S I G 1 9 9 8 3
C1343
C1343
C1349
C1349
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
1
2
1
2
C1344
C1344
C1350
C1350
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
1
2
1
2
S
I G
1
0
3
4
C1345
C1345
2
C1351
C1351
0.1UF/10V
0.1UF/10V
0.01UF/25V
0.01UF/25V
IC111
IC111
H5TQ2G63DFR-PBC
H5TQ2G63DFR-PBC
DDR3 SDRAM
DDR3 SDRAM
[V-MDSD128M16]
[V-MDSD128M16]
M_A_DDR3_A0
M_A_DDR3_A0
N3
S I G 1 7 4 9 4
A0
A0
M_A_DDR3_A1
M_A_DDR3_A1
P7
S I G 1 7 4 9 3
A1
A1
M_A_DDR3_A2
M_A_DDR3_A2
P3
S I G 1 7 4 9 2
A2
A2
M_A_DDR3_A3
M_A_DDR3_A3
N2
S I G 1 7 4 9 1
A3
A3
M_A_DDR3_A4
M_A_DDR3_A4
P8
S I G 1 7 4 9 0
A4
A4
M_A_DDR3_A5
M_A_DDR3_A5
P2
S I G 1 7 4 8 9
A5
A5
M_A_DDR3_A6
M_A_DDR3_A6
R8
S I G 1 7 4 8 8
A6
A6
M_A_DDR3_A7
M_A_DDR3_A7
R2
S I G 1 7 4 8 7
A7
A7
M_A_DDR3_A8
M_A_DDR3_A8
T8
S I G 1 7 4 8 6
A8
A8
M_A_DDR3_A9
M_A_DDR3_A9
R3
S I G 1 7 4 8 5
A9
A9
M_A_DDR3_A10
M_A_DDR3_A10
L7
S I G 1 7 4 8 4
A10/AP
A10/AP
M_A_DDR3_A11
M_A_DDR3_A11
R7
S I G 1 7 4 8 3
A11
A11
M_A_DDR3_A12
M_A_DDR3_A12
N7
S I G 1 7 4 8 2
A12/BC#
A12/BC#
M_A_DDR3_A13
M_A_DDR3_A13
T3
S I G 1 7 4 8 1
A13
A13
M_A_DDR3_A14
M_A_DDR3_A14
T7
NC
NC
M7
NC
NC
M_A_DDR3_BA2
M_A_DDR3_BA2
M3
BA2
BA2
M_A_DDR3_BA1
M_A_DDR3_BA1
N8
BA1
BA1
M_A_DDR3_BA0
M_A_DDR3_BA0
M2
BA0
BA0
M_A_DDR3_MCLKZ
M_A_DDR3_MCLKZ
K7
/CK
/CK
M_A_DDR3_MCLK
M_A_DDR3_MCLK
J7
CK
CK
M_A_DDR3_CKE
M_A_DDR3_CKE
K9
CKE
CKE
L2
/CS
/CS
M_A_DDR3_RASZ
M_A_DDR3_RASZ
J3
/RAS
/RAS
M_A_DDR3_CASZ
M_A_DDR3_CASZ
K3
/CAS
/CAS
M_A_DDR3_WEZ
M_A_DDR3_WEZ
L3
/WE
/WE
S_A_DDR3_DQM2
S_A_DDR3_DQM2
E7
110
DML
DML
S_A_DDR3_DQM3
S_A_DDR3_DQM3
D3
110
DMU
DMU
S_A_DDR3_DQS2
S_A_DDR3_DQS2
F3
110
DQSL
DQSL
S_A_DDR3_DQSB2
S_A_DDR3_DQSB2
G3
110
/DQSL
/DQSL
S_A_DDR3_DQS3
S_A_DDR3_DQS3
110
C7
DQSU
DQSU
S_A_DDR3_DQSB3
S_A_DDR3_DQSB3
B7
110
/DQSU
/DQSU
M_A_DDR3_ODT
M_A_DDR3_ODT
K1
ODT
ODT
M_A_DDR3_RESET
M_A_DDR3_RESET
T2
/RESET
/RESET
R1321
R1321
1
2
L8
S I G 1 0 4 3 5
ZQ
ZQ
240OHM
240OHM
H1
VREFDQ
VREFDQ
0.5%
0.5%
M8
VREFCA
VREFCA
A1
VDDQ
VDDQ
4
A8
0
4
VDDQ
VDDQ
0
1
I G
S
C1
VDDQ
VDDQ
C9
VDDQ
VDDQ
D2
VDDQ
VDDQ
E9
VDDQ
VDDQ
F1
VDDQ
VDDQ
H2
VDDQ
VDDQ
H9
VDDQ
VDDQ
B2
VDD
VDD
D9
VDD
VDD
G7
VDD
VDD
K2
VDD
VDD
K8
VDD
VDD
N1
VDD
VDD
N9
S I G 1 0 3 3 8
VDD
VDD
R1
S I G 1 0 4 3 8
VDD
VDD
R9
VDD
VDD
1.5V
HYNIX/H5TQ2G63DFR-PBC
HYNIX/H5TQ2G63DFR-PBC
C1352
C1352
mx_c0603
mx_c0603
2
1
C1353
C1353
4.7UF/6.3V
4.7UF/6.3V
C1354
C1354
1
2
S I G 1 0 4 3 9
C1355
C1355
1UF/6.3V
1UF/6.3V
S_A_DDR3_DQ16
S_A_DDR3_DQ16
E3
110
DQL0
DQL0
S_A_DDR3_DQ17
S_A_DDR3_DQ17
F7
110
DQL1
DQL1
S_A_DDR3_DQ18
S_A_DDR3_DQ18
F2
110
DQL2
DQL2
S_A_DDR3_DQ19
S_A_DDR3_DQ19
F8
110
DQL3
DQL3
S_A_DDR3_DQ20
S_A_DDR3_DQ20
H3
110
DQL4
DQL4
S_A_DDR3_DQ21
S_A_DDR3_DQ21
H8
110
DQL5
DQL5
S_A_DDR3_DQ22
S_A_DDR3_DQ22
G2
110
DQL6
DQL6
S_A_DDR3_DQ23
S_A_DDR3_DQ23
H7
110
DQL7
DQL7
S_A_DDR3_DQ24
S_A_DDR3_DQ24
D7
110
DQU0
DQU0
S_A_DDR3_DQ25
S_A_DDR3_DQ25
C3
110
DQU1
DQU1
S_A_DDR3_DQ26
S_A_DDR3_DQ26
C8
110
DQU2
DQU2
S_A_DDR3_DQ27
S_A_DDR3_DQ27
C2
110
DQU3
DQU3
S_A_DDR3_DQ28
S_A_DDR3_DQ28
A7
110
DQU4
DQU4
S_A_DDR3_DQ29
S_A_DDR3_DQ29
A2
110
DQU5
DQU5
S_A_DDR3_DQ30
S_A_DDR3_DQ30
B8
110
DQU6
DQU6
S_A_DDR3_DQ31
S_A_DDR3_DQ31
A3
110
DQU7
DQU7
J1
NC
NC
J9
NC
NC
L1
NC
NC
L9
NC
NC
B1
VSSQ
VSSQ
B9
VSSQ
VSSQ
D1
VSSQ
VSSQ
D8
VSSQ
VSSQ
E2
VSSQ
VSSQ
E8
VSSQ
VSSQ
F9
VSSQ
VSSQ
G1
VSSQ
VSSQ
G9
VSSQ
VSSQ
A9
VSS
VSS
B3
VSS
VSS
E1
VSS
VSS
G8
VSS
VSS
J2
VSS
VSS
J8
VSS
VSS
M1
VSS
VSS
M9
VSS
VSS
P1
VSS
VSS
P9
VSS
VSS
T1
VSS
VSS
T9
VSS
VSS
1
2
1000PF/50V
1000PF/50V
1
2
1000PF/50V
1000PF/50V
Title :
Title :
Title :
'
'
'
Engineer:
Engineer:
Engineer:
CVP DM HW
CVP DM HW
CVP DM HW
MAIN BOARD
MAIN BOARD
MAIN BOARD
Size
Size
Size
Project Name
Project Name
Project Name
A3
A3
A3
Date:
Date:
Date:
Tuesday, January 29, 2013
Tuesday, January 29, 2013
Tuesday, January 29, 2013
Sheet
Sheet
Sheet
125
125
125
of
of
of
76
76
76
Rev
Rev
Rev
1.00
1.00
1.00
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