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5. Memory map
&H40000 [ -
:
32K RAM
16 CRAM a
eae
me
eakRam
| SC
card
&H47FFF
&H4FFFF
Py
&HB8000
&HBFFFF
&HEOO0O
Built-in ROM
(128KB)
&HFFFFF
6. LSI description
8K RAM card
BHASFFE
&H41 FFF
1
Output
vec
Power
RESET
input
GND
Power
~
TEST \
Input
Cl
Input
co
Output
ON
Input
WR
Quipyt
MRQ
-
54
KO14
Output
55
KO13
Output
56
KO12
Output
inpwWOupa
KO15
Output
—
Ceramic oscillation output
Ceramic oscillation input
CR oscillation output
CR oscillation input
Display power (converter) control output
© power input terminal
Reset input. Reset at high level.
©power input terminal
Test input
Cassette signal input terminal
Cassette signal output terminal
ON key input terminal. Normally pulled down to low level.
Write clock. Normally high level.
(Not used.)
Key input terminal
Data bus
Address bus
(Not used.)
Clock output terminal for display chip
SIO PRQ (Not used.)
SIO ER, High level with OPEN command.
SIO RR (Reception in the main body side allowed)
SIO RS (Send request in the main body side)
Key: strobe signal
Low battery detection input terminal
Signal description
PC-E500
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